Hi, This patch addresses PR target/113615.
It improves the readability of PTX assembly output by giving meaningful names to special pseudo registers used in OpenMP/OpenACC offloading. Currently, these registers appear with generic names (e.g., %r67), which makes debugging difficult. This patch maps them to descriptive names like %r_unisimt_master. I have tested this change on x86_64-pc-linux-gnu targeting nvptx-none. No new test failures were introduced. Thank you, Amruth --- >From 378b40ba7022b925a0c2f2209886bf3ebfd3048f Mon Sep 17 00:00:00 2001 From: Amruth Tetakali <[email protected]> Date: Mon, 13 Oct 2025 22:04:37 +0530 Subject: [PATCH] nvptx: Add meaningful names to special pseudo registers [PR113615] The NVPTX backend uses special pseudo registers for OpenMP/OpenACC features like SIMT execution, reductions, and broadcasts. These currently appear in PTX assembly output with generic names like %r67, %r68, making debugging difficult. This patch modifies output_reg() to detect these special registers and output meaningful names: - unisimt_outside_simt_predicate -> %r_outside_simt_p - unisimt_master -> %r_unisimt_master - unisimt_predicate -> %r_unisimt_predicate - axis_predicate[0/1] -> %r_axis_predicate_0/1 - bcast_partition -> %r_bcast_partition - red_partition -> %r_red_partition - sync_bar -> %r_sync_bar - unisimt_location -> %r_unisimt_location This improves PTX assembly readability for developers debugging OpenMP/OpenACC offloading code. tested on x86_64-pc-linux-gnu with nvptx-none target. No new test failures were introduced. gcc/ PR target/113615 * config/nvptx/nvptx.cc (output_reg): Add meaningful names for special pseudo registers used in OpenMP/OpenACC offloading. --- gcc/config/nvptx/nvptx.cc | 65 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc index a92a1e391c6..f539009b10f 100644 --- a/gcc/config/nvptx/nvptx.cc +++ b/gcc/config/nvptx/nvptx.cc @@ -588,7 +588,70 @@ output_reg (FILE *file, unsigned regno, machine_mode inner_mode, if (HARD_REGISTER_NUM_P (regno)) fprintf (file, "%s", reg_names[regno]); else - fprintf (file, "%%r%d", regno); + { + bool is_special = false; + + if (cfun && cfun->machine) + { + if (cfun->machine->unisimt_outside_simt_predicate + && regno == REGNO (cfun->machine->unisimt_outside_simt_predicate)) + { + fprintf (file, "%%r_outside_simt_p"); + is_special = true; + } + else if (cfun->machine->unisimt_master + && regno == REGNO (cfun->machine->unisimt_master)) + { + fprintf (file, "%%r_unisimt_master"); + is_special = true; + } + else if (cfun->machine->unisimt_predicate + && regno == REGNO (cfun->machine->unisimt_predicate)) + { + fprintf (file, "%%r_unisimt_predicate"); + is_special = true; + } + else if (cfun->machine->axis_predicate[0] + && regno == REGNO (cfun->machine->axis_predicate[0])) + { + fprintf (file, "%%r_axis_predicate_0"); + is_special = true; + } + else if (cfun->machine->axis_predicate[1] + && regno == REGNO (cfun->machine->axis_predicate[1])) + { + fprintf (file, "%%r_axis_predicate_1"); + is_special = true; + } + else if (cfun->machine->bcast_partition + && regno == REGNO (cfun->machine->bcast_partition)) + { + fprintf (file, "%%r_bcast_partition"); + is_special = true; + } + else if (cfun->machine->red_partition + && regno == REGNO (cfun->machine->red_partition)) + { + fprintf (file, "%%r_red_partition"); + is_special = true; + } + else if (cfun->machine->sync_bar + && regno == REGNO (cfun->machine->sync_bar)) + { + fprintf (file, "%%r_sync_bar"); + is_special = true; + } + else if (cfun->machine->unisimt_location + && regno == REGNO (cfun->machine->unisimt_location)) + { + fprintf (file, "%%r_unisimt_location"); + is_special = true; + } + } + + if (!is_special) + fprintf (file, "%%r%d", regno); + } } else if (subreg_offset >= 0) { -- 2.43.0
