> -----Original Message-----
> From: Jennifer Schmitz <[email protected]>
> Sent: 21 October 2025 08:30
> To: Richard Sandiford <[email protected]>
> Cc: Kyrylo Tkachov <[email protected]>; GCC Patches <gcc-
> [email protected]>; Tamar Christina <[email protected]>; Alex
> Coplan <[email protected]>; Richard Earnshaw
> <[email protected]>; Andrew Pinski <[email protected]>
> Subject: Re: [PATCH][PR121599] aarch64: Fix ICE when op2 is zero for SVE2
> saturating add intrinsics.
>
>
>
> > On 6 Oct 2025, at 16:26, Jennifer Schmitz <[email protected]> wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> >> On 2 Oct 2025, at 23:09, Richard Sandiford
> <[email protected]> wrote:
> >>
> >> External email: Use caution opening links or attachments
> >>
> >>
> >> Jennifer Schmitz <[email protected]> writes:
> >>> diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
> b/gcc/config/aarch64/aarch64-sve-builtins.cc
> >>> index 22d75197188..5efc5ba3846 100644
> >>> --- a/gcc/config/aarch64/aarch64-sve-builtins.cc
> >>> +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
> >>> @@ -4356,7 +4356,11 @@ function_expander::use_cond_insn
> (insn_code icode, unsigned int merge_argno)
> >>> add_input_operand (icode, pred);
> >>> for (unsigned int i = 0; i < nops; ++i)
> >>> add_input_operand (icode, args[opno + i]);
> >>> - add_input_operand (icode, fallback_arg);
> >>> + if (insn_operand_matches (icode, opno + nops + 1, fallback_arg)
> >>
> >> "m_ops.length ()" would be more direct than "opno + nops + 1"
> >>
> >>> + && fallback_arg == CONST0_RTX (mode))
> >>
> >> Very minor, sorry, but: IMO it's more natural (and should be cheaper)
> >> to test this first and insn_operand_matches second.
> >>
> >> OK with those changes from my POV, but please leave a day or so for
> >> others to comment. As far as backports go: IMO it's good for GCC 15
> >> and GCC 14. Not sure whether it's important enough to risk GCC 13,
> >> given that the next release in the series will be the last.
> > Thanks, I made the changes and pushed it to trunk
> (9b102d2e1e3..ad2991b2749).
> > I also tested the patch on releases/gcc-15 and releases/gcc-14, no
> regression.
> > OK to backport it to GCC15 and GCC14?
Ok for 14 an 15.
Thanks,
Tamar
> > Thanks,
> > Jennifer
> Gentle ping.
> Thanks,
> Jennifer
> >>
> >> Thanks,
> >> Richard
> >>
> >>> + add_fixed_operand (fallback_arg);
> >>> + else
> >>> + add_input_operand (icode, fallback_arg);
> >>> return generate_insn (icode);
> >>> }
> >>>
> >>> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
> b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
> >>> new file mode 100644
> >>> index 00000000000..90c5ac97e4f
> >>> --- /dev/null
> >>> +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
> >>> @@ -0,0 +1,31 @@
> >>> +/* PR target/121599. */
> >>> +/* { dg-do compile } */
> >>> +/* { dg-options "-O2" } */
> >>> +/* { dg-final { check-function-bodies "**" "" "" } } */
> >>> +
> >>> +#include <arm_sve.h>
> >>> +
> >>> +/*
> >>> +** foo:
> >>> +** movi d([0-9]+), #0
> >>> +** movprfx z0\.b, p0/z, z0\.b
> >>> +** usqadd z0\.b, p0/m, z0\.b, z\1\.b
> >>> +** ret
> >>> +*/
> >>> +svuint8_t foo (svbool_t pg, svuint8_t op1)
> >>> +{
> >>> + return svsqadd_u8_z (pg, op1, svdup_s8 (0));
> >>> +}
> >>> +
> >>> +/*
> >>> +** bar:
> >>> +** movi d([0-9]+), #0
> >>> +** movprfx z0\.b, p0/z, z0\.b
> >>> +** suqadd z0\.b, p0/m, z0\.b, z\1\.b
> >>> +** ret
> >>> +*/
> >>> +svint8_t bar (svbool_t pg, svint8_t op1)
> >>> +{
> >>> + return svuqadd_n_s8_z (pg, op1, 0);
> >>> +}
> >>> +
>
