On 24/10/2025 06:15, Avinash Jayakar wrote:
Thanks for the info. I also was able to build and debug it for this
target.
For the signed mod case, there is an extra requirement for
vectorization that is to have vector operation support for ABS_EXPR,
which amdgcn does not have.
5033 if (!unsigned_p)
5034 {
5035 // check availibility of abs expression for vector
5036 if (!target_has_vecop_for_code (ABS_EXPR, vectype))
5037 return NULL;
(1) Either we could modify the test case to check if target supports
vector absolute expression like we did for vect_condition.
I am not sure how to do that for now. In target-supports.exp, I do not
see any keyword to use in the test to check if target supports vector
absolute expression.
(2) Or better yet if a target does not support ABS_EXPR we could
fallback to implementing the absolute expression using vectorized
statements
a < 0 ? -a : a; (LT_EXPR, COND_EXPR and NEGATE_EXPR). This would
increase the statements, but the cost analysis of vectorized could
decide in choosing vector vs scalar implementation.
Please do let me know in case you need help in resolving this, I can
submit a patch with the required changes for the second case.
I've just pushed a patch for this (attached). In fact I found that the
hardware cannot do integer ABS in one instruction, but the masked
instruction sequence in the backend is probably better than the
subtract-and-merge the vectorizer will do.
The issue should be fixed now.
Andrew
From 71c158ad22df895c379a2f539fde0f76d421e0be Mon Sep 17 00:00:00 2001
From: Andrew Stubbs <[email protected]>
Date: Fri, 24 Oct 2025 10:41:40 +0000
Subject: [PATCH] amdgcn: Implement vector ABS_EXPR for integers (PR104116)
There's not a single vector instruction for integer absolute, but this
enables the optimization in PR104116, and is probably useful otherwise.
The pr104116-*.c testcases should now pass on amdgcn.
gcc/ChangeLog:
PR tree-optimization/104116
* config/gcn/gcn-valu.md (abs<mode>2): New define_expand for
integer vector modes.
---
gcc/config/gcn/gcn-valu.md | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index a34d2e30c97..96c183d67b6 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -3128,6 +3128,20 @@ (define_insn_and_split "one_cmpl<mode>2<exec>"
}
[(set_attr "type" "mult")])
+(define_expand "abs<mode>2"
+ [(set (match_operand:V_INT 0 "register_operand")
+ (abs:V_INT (match_operand:V_INT 1 "register_operand")))]
+ ""
+ {
+ rtx vcc = gen_reg_rtx (DImode);
+ rtx zero = gcn_vec_constant (<MODE>mode, 0);
+ emit_insn (gen_vec_cmp<mode>di (vcc, gen_rtx_LT (VOIDmode, 0, 0),
+ operands[1], zero));
+ emit_insn (gen_sub<mode>3_exec (operands[0], zero, operands[1],
+ operands[1], vcc));
+ DONE;
+ })
+
;; }}}
;; {{{ FP binops - special cases
--
2.51.0
