This patch implements _BitInt support for RISC-V target by defining the
type layout and ABI requirements. The limb mode selection is based on
the bit width, using appropriate integer modes from QImode to TImode.
The implementation also adds the necessary libgcc version symbols for
_BitInt runtime support functions.
gcc/ChangeLog:
PR target/117581
* config/riscv/riscv.cc (riscv_bitint_type_info): New function.
(TARGET_C_BITINT_TYPE_INFO): Define.
gcc/testsuite/ChangeLog:
PR target/117581
* gcc.target/riscv/bitint-32-on-rv64.c: New test.
* gcc.target/riscv/bitint-alignments.c: New test.
* gcc.target/riscv/bitint-args.c: New test.
* gcc.target/riscv/bitint-sizes.c: New test.
libgcc/ChangeLog:
PR target/117581
* config/riscv/libgcc-riscv.ver: New file.
* config/riscv/t-elf (SHLIB_MAPFILES): Add libgcc-riscv.ver.
* config/riscv/t-softfp32 (softfp_extras): Add floatbitinttf and
fixtfbitint.
---
gcc/config/riscv/riscv.cc | 32 ++++++++
.../gcc.target/riscv/bitint-32-on-rv64.c | 47 +++++++++++
.../gcc.target/riscv/bitint-alignments.c | 60 ++++++++++++++
gcc/testsuite/gcc.target/riscv/bitint-args.c | 82 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/bitint-sizes.c | 65 +++++++++++++++
libgcc/config/riscv/libgcc-riscv.ver | 28 +++++++
libgcc/config/riscv/t-elf | 2 +
libgcc/config/riscv/t-softfp32 | 2 +
8 files changed, 318 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/bitint-32-on-rv64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/bitint-alignments.c
create mode 100644 gcc/testsuite/gcc.target/riscv/bitint-args.c
create mode 100644 gcc/testsuite/gcc.target/riscv/bitint-sizes.c
create mode 100644 libgcc/config/riscv/libgcc-riscv.ver
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e186c6a99e9..2a33aeafa21 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -14654,6 +14654,35 @@ riscv_c_mode_for_floating_type (enum tree_index ti)
return default_mode_for_floating_type (ti);
}
+/* Implement TARGET_C_BITINT_TYPE_INFO.
+ Return true if _BitInt(N) is supported and fill its details into *INFO. */
+bool
+riscv_bitint_type_info (int n, struct bitint_info *info)
+{
+ if (n <= 8)
+ info->limb_mode = QImode;
+ else if (n <= 16)
+ info->limb_mode = HImode;
+ else if (n <= 32)
+ info->limb_mode = SImode;
+ else if (n <= 64)
+ info->limb_mode = DImode;
+ else
+ {
+ if (TARGET_64BIT)
+ info->limb_mode = TImode;
+ else
+ info->limb_mode = DImode;
+ }
+
+ info->abi_limb_mode = info->limb_mode;
+
+ info->big_endian = TARGET_BIG_ENDIAN;
+ info->extended = true;
+ return true;
+}
+
+
/* This parses the version string STR and modifies the feature mask and
priority required to select those targets.
If LOC is nonnull, report diagnostics against *LOC, otherwise
@@ -16633,6 +16662,9 @@ riscv_prefetch_offset_address_p (rtx x, machine_mode
mode)
#undef TARGET_C_MODE_FOR_FLOATING_TYPE
#define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type
+#undef TARGET_C_BITINT_TYPE_INFO
+#define TARGET_C_BITINT_TYPE_INFO riscv_bitint_type_info
+
#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
riscv_use_by_pieces_infrastructure_p
diff --git a/gcc/testsuite/gcc.target/riscv/bitint-32-on-rv64.c
b/gcc/testsuite/gcc.target/riscv/bitint-32-on-rv64.c
new file mode 100644
index 00000000000..d37e1a880fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/bitint-32-on-rv64.c
@@ -0,0 +1,47 @@
+/* { dg-do compile { target bitint } } */
+/* { dg-additional-options "-march=rv64gc -mabi=lp64d -std=c23 -O
-fno-stack-clash-protection -g -mcmodel=medlow" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" "-O0"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+signed _BitInt(32) a;
+unsigned _BitInt(32) b;
+signed _BitInt(16) c;
+unsigned _BitInt(16) d;
+
+signed _BitInt(32) f1(void) {
+/*
+** f1:
+** ...
+** lw a0,%lo\(a\)\([ats][0-9]+\)
+** ret
+*/
+ return a;
+}
+unsigned _BitInt(32) f2(void) {
+/*
+** f2:
+** ...
+** lw a0,%lo\(b\)\([ats][0-9]+\)
+** ret
+*/
+ return b;
+}
+
+signed _BitInt(16) f3(void) {
+/*
+** f3:
+** ...
+** lh a0,%lo\(c\)\([ats][0-9]+\)
+** ret
+*/
+ return c;
+}
+unsigned _BitInt(16) f4(void) {
+/*
+** f4:
+** ...
+** lhu a0,%lo\(d\)\([ats][0-9]+\)
+** ret
+*/
+ return d;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/bitint-alignments.c
b/gcc/testsuite/gcc.target/riscv/bitint-alignments.c
new file mode 100644
index 00000000000..01cc41eb88d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/bitint-alignments.c
@@ -0,0 +1,60 @@
+/* { dg-do run { target bitint } } */
+/* { dg-additional-options "-std=c23" } */
+
+static long unsigned int
+calc_alignof (int n)
+{
+#if __riscv_xlen == 64
+ if (n > 64)
+ return alignof(__int128_t);
+#endif
+ if (n > 32)
+ return alignof(long long);
+ if (n > 16)
+ return alignof(int);
+ if (n > 8)
+ return alignof(short);
+ else
+ return alignof(char);
+}
+
+#define CHECK_ALIGNMENT(N) \
+ if (alignof(_BitInt(N)) != calc_alignof(N)) \
+ __builtin_abort ();
+
+int main (void)
+{
+ CHECK_ALIGNMENT(2);
+ CHECK_ALIGNMENT(3);
+ CHECK_ALIGNMENT(7);
+ CHECK_ALIGNMENT(8);
+ CHECK_ALIGNMENT(9);
+ CHECK_ALIGNMENT(13);
+ CHECK_ALIGNMENT(15);
+ CHECK_ALIGNMENT(16);
+ CHECK_ALIGNMENT(17);
+ CHECK_ALIGNMENT(24);
+ CHECK_ALIGNMENT(31);
+ CHECK_ALIGNMENT(32);
+ CHECK_ALIGNMENT(33);
+ CHECK_ALIGNMENT(42);
+ CHECK_ALIGNMENT(53);
+ CHECK_ALIGNMENT(63);
+ CHECK_ALIGNMENT(64);
+ CHECK_ALIGNMENT(65);
+ CHECK_ALIGNMENT(79);
+ CHECK_ALIGNMENT(96);
+ CHECK_ALIGNMENT(113);
+ CHECK_ALIGNMENT(127);
+ CHECK_ALIGNMENT(128);
+ CHECK_ALIGNMENT(129);
+ CHECK_ALIGNMENT(153);
+ CHECK_ALIGNMENT(255);
+ CHECK_ALIGNMENT(256);
+ CHECK_ALIGNMENT(257);
+ CHECK_ALIGNMENT(353);
+ CHECK_ALIGNMENT(512);
+ CHECK_ALIGNMENT(620);
+ CHECK_ALIGNMENT(1024);
+ CHECK_ALIGNMENT(30000);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/bitint-args.c
b/gcc/testsuite/gcc.target/riscv/bitint-args.c
new file mode 100644
index 00000000000..eacddc40bd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/bitint-args.c
@@ -0,0 +1,82 @@
+/* { dg-do compile { target bitint } } */
+/* { dg-additional-options "-march=rv64gc -mabi=lp64d -std=c23 -O
-fno-stack-clash-protection -g" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" "-O0"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#define CHECK_ARG(N) \
+void f##N(_BitInt(N) *ptr, _BitInt(N) y) \
+{ \
+ *ptr = y; \
+}
+
+
+CHECK_ARG(2)
+/*
+** f2:
+** sb a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(8)
+/*
+** f8:
+** sb a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(9)
+/*
+** f9:
+** sh a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(16)
+/*
+** f16:
+** sh a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(19)
+/*
+** f19:
+** sw a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(32)
+/*
+** f32:
+** sw a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(42)
+/*
+** f42:
+** sd a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(64)
+/*
+** f64:
+** sd a1,0\(a0\)
+** ret
+*/
+CHECK_ARG(65)
+/*
+** f65:
+** sd a1,0\(a0\)
+** sd a2,8\(a0\)
+** ret
+*/
+CHECK_ARG(127)
+/*
+** f127:
+** sd a1,0\(a0\)
+** sd a2,8\(a0\)
+** ret
+*/
+
+CHECK_ARG(128)
+/*
+** f128:
+** sd a1,0\(a0\)
+** sd a2,8\(a0\)
+** ret
+*/
diff --git a/gcc/testsuite/gcc.target/riscv/bitint-sizes.c
b/gcc/testsuite/gcc.target/riscv/bitint-sizes.c
new file mode 100644
index 00000000000..6cdb746e3a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/bitint-sizes.c
@@ -0,0 +1,65 @@
+/* { dg-do run { target bitint } } */
+/* { dg-additional-options "-std=c23" } */
+
+static long unsigned int
+calc_size (int n)
+{
+#if __riscv_xlen == 64
+ if (n > 128)
+ return ((n - 1)/128 + 1) * sizeof(__int128_t);
+ if (n > 64)
+ return sizeof(__int128_t);
+#elif __riscv_xlen == 32
+ if (n > 64)
+ return ((n - 1)/64 + 1) * sizeof(long long);
+#endif
+ if (n > 32)
+ return sizeof(long long);
+ if (n > 16)
+ return sizeof(int);
+ if (n > 8)
+ return sizeof(short);
+ else
+ return sizeof(char);
+}
+
+#define CHECK_SIZE(N) \
+ if (sizeof(_BitInt(N)) != calc_size(N)) \
+ __builtin_abort ();
+
+int main (void)
+{
+ CHECK_SIZE(2);
+ CHECK_SIZE(3);
+ CHECK_SIZE(7);
+ CHECK_SIZE(8);
+ CHECK_SIZE(9);
+ CHECK_SIZE(13);
+ CHECK_SIZE(15);
+ CHECK_SIZE(16);
+ CHECK_SIZE(17);
+ CHECK_SIZE(24);
+ CHECK_SIZE(31);
+ CHECK_SIZE(32);
+ CHECK_SIZE(33);
+ CHECK_SIZE(42);
+ CHECK_SIZE(53);
+ CHECK_SIZE(63);
+ CHECK_SIZE(64);
+ CHECK_SIZE(65);
+ CHECK_SIZE(79);
+ CHECK_SIZE(96);
+ CHECK_SIZE(113);
+ CHECK_SIZE(127);
+ CHECK_SIZE(128);
+ CHECK_SIZE(129);
+ CHECK_SIZE(153);
+ CHECK_SIZE(255);
+ CHECK_SIZE(256);
+ CHECK_SIZE(257);
+ CHECK_SIZE(353);
+ CHECK_SIZE(512);
+ CHECK_SIZE(620);
+ CHECK_SIZE(1024);
+ CHECK_SIZE(30000);
+}
diff --git a/libgcc/config/riscv/libgcc-riscv.ver
b/libgcc/config/riscv/libgcc-riscv.ver
new file mode 100644
index 00000000000..0a71f2ecca2
--- /dev/null
+++ b/libgcc/config/riscv/libgcc-riscv.ver
@@ -0,0 +1,28 @@
+# Copyright (C) 2025 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+GCC_16.0.0 {
+ __mulbitint3
+ __divmodbitint4
+ __fixsfbitint
+ __fixdfbitint
+ __fixtfbitint
+ __floatbitintsf
+ __floatbitintdf
+ __floatbitinttf
+}
diff --git a/libgcc/config/riscv/t-elf b/libgcc/config/riscv/t-elf
index acb5e280676..c0c73dd57bc 100644
--- a/libgcc/config/riscv/t-elf
+++ b/libgcc/config/riscv/t-elf
@@ -7,3 +7,5 @@ LIB2ADD += $(srcdir)/config/riscv/save-restore.S \
# Avoid the full unwinder being pulled along with the division libcalls.
LIB2_DIVMOD_EXCEPTION_FLAGS := -fasynchronous-unwind-tables
+
+SHLIB_MAPFILES += $(srcdir)/config/riscv/libgcc-riscv.ver
diff --git a/libgcc/config/riscv/t-softfp32 b/libgcc/config/riscv/t-softfp32
index da55eb348c1..710145d9f2c 100644
--- a/libgcc/config/riscv/t-softfp32
+++ b/libgcc/config/riscv/t-softfp32
@@ -34,6 +34,8 @@ endif
endif
+softfp_extras += floatbitinttf fixtfbitint
+
else
# ABI_QUAD
--
2.34.1
