We have multiple cpus with different abis (combinations of 32 vs 64, float vs
no-float, etc). It's annoying having to specify both -mcpu=thing and the
correct -mabi=thing. Just as with -mcpu selecting a default ISA set, this adds
smarts for it to select a default ABI.
You can still specify -mabi if you want to go off-road, but this gives us one
source of truth. It's possible I've made a mistake with selecting the default
abi for the current set of cpus.
Also while there, cleaned up riscv_expend_arch_from_cpu. I found it over
complex, and as it's potentially getting data from a user-provided specs file,
best not to use asserts for errors, just fail safely.
nathan
--
Nathan Sidwell
From 4ae4af17882c2e21b46f3486f68d213498d1c54b Mon Sep 17 00:00:00 2001
From: Nathan Sidwell <[email protected]>
Date: Sat, 1 Nov 2025 20:17:04 -0400
Subject: [PATCH] Riscv: Per-cpu default ABI
Per-cpu abis are helpful when supporting multiple cpus with different
ABIs.
gcc/
* common/config/rsicv/riscv-common.cc (riscv_cpu_tables): Adjust
RISCV_CORE definition.
(riscv_expand_arch_from_cpu): Simplify.
(riscv_expand_abi_from_cpu): New.
* config/riscv/gen-riscv-mcpu-texi.cc (main): Adjust RISCV_CORE
definition.
* config/riscv/risdcv-cores.def: Add per-cpu default ABI.
* config/riscv/riscv-protos.h (struct riscv_cpu_info): Add
per-cpu default ABI.
* config/riscv/riscv.h (riscv_expand_abi_from_cpu): Declare.
(EXTRA_SPEC_FUNCTIONS): Add it.
(OPTION_DEFAULT_SPECS): Default abi from cpu.
(DRIVER_SELF_SPECS): Likewise.
---
gcc/common/config/riscv/riscv-common.cc | 53 ++++++++++++++---------
gcc/config/riscv/gen-riscv-mcpu-texi.cc | 2 +-
gcc/config/riscv/riscv-cores.def | 56 ++++++++++++-------------
gcc/config/riscv/riscv-protos.h | 3 ++
gcc/config/riscv/riscv.h | 9 +++-
5 files changed, 72 insertions(+), 51 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index adfd22019a9..b0d6da5537a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -281,10 +281,10 @@ static const riscv_profiles riscv_profiles_table[] =
static const riscv_cpu_info riscv_cpu_tables[] =
{
-#define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
- {CORE_NAME, ARCH, TUNE},
+#define RISCV_CORE(CORE_NAME, ARCH, ABI, TUNE) \
+ {CORE_NAME, ARCH, ABI, TUNE},
#include "../../../config/riscv/riscv-cores.def"
- {NULL, NULL, NULL}
+ {NULL, NULL, NULL, NULL}
};
static const char *riscv_tunes[] =
@@ -1810,34 +1810,47 @@ riscv_default_mtune (int argc, const char **argv)
/* Expand arch string with implied extensions from -mcpu option. */
const char *
-riscv_expand_arch_from_cpu (int argc ATTRIBUTE_UNUSED,
- const char **argv)
+riscv_expand_arch_from_cpu (int argc, const char **argv)
{
- gcc_assert (argc > 0 && argc <= 2);
- const char *default_arch_str = NULL;
- const char *arch_str = NULL;
- if (argc >= 2)
- default_arch_str = argv[1];
+ const char *arch_str = nullptr;
- const riscv_cpu_info *cpu = riscv_find_cpu (argv[0]);
+ if (argc > 0)
+ if (const riscv_cpu_info *cpu = riscv_find_cpu (argv[0]))
+ arch_str = cpu->arch;
- if (cpu == NULL)
+ if (!arch_str)
{
- if (default_arch_str == NULL)
+ if (argc < 2)
return "";
- else
- arch_str = default_arch_str;
+ arch_str = argv[1];
}
- else
- arch_str = cpu->arch;
- location_t loc = UNKNOWN_LOCATION;
-
- riscv_parse_arch_string (arch_str, NULL, loc);
+ riscv_parse_arch_string (arch_str, NULL, UNKNOWN_LOCATION);
const std::string arch = riscv_arch_str (false);
return xasprintf ("-march=%s", arch.c_str());
}
+/* Expand abi string from -mcpu option. */
+
+const char *
+riscv_expand_abi_from_cpu (int argc, const char **argv)
+{
+ const char *abi_str = nullptr;
+
+ if (argc > 0)
+ if (const riscv_cpu_info *cpu = riscv_find_cpu (argv[0]))
+ abi_str = cpu->abi;
+
+ if (!abi_str)
+ {
+ if (argc < 2)
+ return "";
+ abi_str = argv[1];
+ }
+
+ return xasprintf ("-mabi=%s", abi_str);
+}
+
/* Report error if not found suitable multilib. */
const char *
riscv_multi_lib_check (int argc ATTRIBUTE_UNUSED,
diff --git a/gcc/config/riscv/gen-riscv-mcpu-texi.cc b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
index 9681438fb9f..bcc820cda8e 100644
--- a/gcc/config/riscv/gen-riscv-mcpu-texi.cc
+++ b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
@@ -26,7 +26,7 @@ main ()
std::vector<std::string> coreNames;
-#define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH) \
+#define RISCV_CORE(CORE_NAME, ARCH, ABI, MICRO_ARCH) \
coreNames.push_back (CORE_NAME);
#include "riscv-cores.def"
#undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index cc9d5c03cb8..6a8d01f2464 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -60,7 +60,7 @@ RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)
Before using #include to read this file, define a macro:
- RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
+ RISCV_CORE(CORE_NAME, ARCH, ABI, MICRO_ARCH)
The CORE_NAME is the name of the core, represented as a string.
The ARCH is the default arch of the core, represented as a string,
@@ -69,57 +69,57 @@ RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)
will be made, represented as an identifier. */
#ifndef RISCV_CORE
-#define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
+#define RISCV_CORE(CORE_NAME, ARCH, ABI, MICRO_ARCH)
#endif
-RISCV_CORE("sifive-e20", "rv32imc", "rocket")
-RISCV_CORE("sifive-e21", "rv32imac", "rocket")
-RISCV_CORE("sifive-e24", "rv32imafc", "rocket")
-RISCV_CORE("sifive-e31", "rv32imac", "sifive-3-series")
-RISCV_CORE("sifive-e34", "rv32imafc", "sifive-3-series")
-RISCV_CORE("sifive-e76", "rv32imafc", "sifive-7-series")
+RISCV_CORE("sifive-e20", "rv32imc", "ilp32", "rocket")
+RISCV_CORE("sifive-e21", "rv32imac", "ilp32", "rocket")
+RISCV_CORE("sifive-e24", "rv32imafc", "ilp32f", "rocket")
+RISCV_CORE("sifive-e31", "rv32imac", "ilp32", "sifive-3-series")
+RISCV_CORE("sifive-e34", "rv32imafc", "ilp32f", "sifive-3-series")
+RISCV_CORE("sifive-e76", "rv32imafc", "ilp32f", "sifive-7-series")
-RISCV_CORE("sifive-s21", "rv64imac", "rocket")
-RISCV_CORE("sifive-s51", "rv64imac", "sifive-5-series")
-RISCV_CORE("sifive-s54", "rv64imafdc", "sifive-5-series")
-RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
+RISCV_CORE("sifive-s21", "rv64imac", "lp64", "rocket")
+RISCV_CORE("sifive-s51", "rv64imac", "lp64", "sifive-5-series")
+RISCV_CORE("sifive-s54", "rv64imafdc", "lp64d", "sifive-5-series")
+RISCV_CORE("sifive-s76", "rv64imafdc", "lp64d", "sifive-7-series")
-RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
-RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
-RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series")
+RISCV_CORE("sifive-u54", "rv64imafdc", "lp64d", "sifive-5-series")
+RISCV_CORE("sifive-u74", "rv64imafdc", "lp64d", "sifive-7-series")
+RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "lp64d", "sifive-7-series")
RISCV_CORE("sifive-p450", "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_"
"ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
"zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs",
- "sifive-p400-series")
+ "lp64d", "sifive-p400-series")
RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_"
"ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
"zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_"
"zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg",
- "sifive-p600-series")
+ "lp64d", "sifive-p600-series")
RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
"xtheadmemidx_xtheadmempair_xtheadsync",
- "thead-c906")
+ "lp64d", "thead-c906")
RISCV_CORE("xt-c908", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_"
"zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
"sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_"
"xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
"xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync",
- "xt-c908")
+ "lp64d", "xt-c908")
RISCV_CORE("xt-c908v", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_"
"zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
"zvfh_sstc_svinval_svnapot_svpbmt__xtheadba_"
"xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_"
"xtheadfmemidx_xtheadmac_xtheadmemidx_"
"xtheadmempair_xtheadsync",
- "xt-c908")
+ "lp64d", "xt-c908")
RISCV_CORE("xt-c910", "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
"xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
"xtheadmemidx_xtheadmempair_xtheadsync",
- "xt-c910")
+ "lp64d", "xt-c910")
RISCV_CORE("xt-c910v2", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_"
"zicsr_zifencei_zihintntl_zihintpause_zihpm_"
"zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
@@ -127,13 +127,13 @@ RISCV_CORE("xt-c910v2", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_"
"xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
"xtheadmemidx_xtheadmempair_xtheadsync",
- "xt-c910v2")
+ "lp64d", "xt-c910v2")
RISCV_CORE("xt-c920", "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
"xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
"xtheadmemidx_xtheadmempair_xtheadsync_"
"xtheadvector",
- "xt-c910")
+ "lp64d", "xt-c910")
RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_"
"zicsr_zifencei_zihintntl_zihintpause_zihpm_"
"zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
@@ -142,19 +142,19 @@ RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_"
"xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
"xtheadmac_xtheadmemidx_xtheadmempair_"
"xtheadsync",
- "xt-c920v2")
+ "lp64d", "xt-c920v2")
RISCV_CORE("tt-ascalon-d8", "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
"ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
"zifencei_zihintntl_zihintpause_zimop_za64rs_"
"zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_"
"zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b",
- "tt-ascalon-d8")
+ "lp64d", "tt-ascalon-d8")
RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_"
"zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
"svinval_zicbom_zicboz",
- "xiangshan-nanhu")
+ "lp64d", "xiangshan-nanhu")
RISCV_CORE("xiangshan-kunminghu", "rv64imafdcbvh_sdtrig_sha_shcounterenw_"
"shgatpa_shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd_"
@@ -167,8 +167,8 @@ RISCV_CORE("xiangshan-kunminghu", "rv64imafdcbvh_sdtrig_sha_shcounterenw_"
"zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintpause_"
"zihpm_zimop_zkn_zknd_zkne_zknh_zksed_zksh_zkt_zvbb_zvfh_"
"zvfhmin_zvkt_zvl128b_zvl32b_zvl64b",
- "xiangshan-kunminghu")
+ "lp64d", "xiangshan-kunminghu")
RISCV_CORE("mips-p8700", "rv64imfd_zicsr_zifencei_zalrsc_zba_zbb",
- "mips-p8700")
+ "lp64d", "mips-p8700")
#undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index cdb706ab82a..3f6cc829209 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -223,6 +223,9 @@ struct riscv_cpu_info {
/* Default arch for this CPU, could be NULL if no default arch. */
const char *arch;
+ /* Default ABI for this CPU, can be nullptr if no default abi. */
+ const char *abi;
+
/* Which automaton to use for tuning. */
const char *tune;
};
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index a0ad75c765a..74892c63635 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -48,11 +48,13 @@ along with GCC; see the file COPYING3. If not see
extern const char *riscv_expand_arch (int argc, const char **argv);
extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
+extern const char *riscv_expand_abi_from_cpu (int argc, const char **argv);
extern const char *riscv_default_mtune (int argc, const char **argv);
extern const char *riscv_multi_lib_check (int argc, const char **argv);
extern const char *riscv_arch_help (int argc, const char **argv);
# define EXTRA_SPEC_FUNCTIONS \
+ { "riscv_expand_abi_from_cpu", riscv_expand_abi_from_cpu }, \
{ "riscv_expand_arch", riscv_expand_arch }, \
{ "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \
{ "riscv_default_mtune", riscv_default_mtune }, \
@@ -74,7 +76,9 @@ extern const char *riscv_arch_help (int argc, const char **argv);
{"arch", "%{!march=*|march=unset:" \
" %{!mcpu=*:-march=%(VALUE)}" \
" %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
- {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
+ {"abi", "%{!mabi=*:" \
+ " %{!mcpu=*:-mabi=%(VALUE)}" \
+ " %{mcpu=*:%:riscv_expand_abi_from_cpu(%* %(VALUE))}}" }, \
{"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
{"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, \
@@ -123,7 +127,8 @@ ARCH_UNSET_CLEANUP_SPECS \
"%{-print-supported-extensions:%:riscv_arch_help()} " \
"%{march=*:%:riscv_expand_arch(%*)} " \
"%{!march=*|march=unset:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " \
-"%{march=unset:%{!mcpu=*:%eAt least one valid -mcpu option must be given after -march=unset}} "
+"%{march=unset:%{!mcpu=*:%eAt least one valid -mcpu option must be given after -march=unset}} " \
+"%{!mabi=*:%{mcpu=*:%:riscv_expand_abi_from_cpu(%*)}} "
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""
--
2.51.1
