[PATCH v1 0/2] Add test cases for vmseq.vx combine on GR2VR cost

[pan2 . li]

From: Pan Li <pan2...@intel.com>

There is no additional change for supporting the vmseq.vx combination on
GR2VR cost.  thus add test cases to ensure it works well as expected.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

Pan Li (2):
  RISC-V: Add test for vec_duplicate + vmseq.vv combine case 0 with GR2VR cost 
0, 1 and 15
  RISC-V: Add test for vec_duplicate + vmseq.vv combine case 1 with GR2VR cost 
0, 1 and 15

 .../riscv/rvv/autovec/vx_vf/vx-1-i16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx_binary.h       |   2 +
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h  | 272 ++++++++++++++++++
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-i16.c    |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-i32.c    |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-i64.c    |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-i8.c     |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c    |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c    |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c    |  15 +
 .../rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c     |  15 +
 34 files changed, 418 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-u8.c

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2.43.0