From: Jiajie Chen <[email protected]>
The current addsi3 define_expand requires loongarch64 to work, but the
existing way of specifying the requirement forbids whole addsi3
generation for loongarch32. Move target bitness check to expand
preparation statments to allow it to fallback to *addsi3 define_insn.
gcc/ChangeLog:
* config/loongarch/loongarch.md (addsi3): Move target bitness
check to if-else for loongarch32.
---
gcc/config/loongarch/loongarch.md | 47 ++++++++++++++++---------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 625f30ca265..5b12763a834 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -742,30 +742,33 @@ (define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r")
(match_operand:SI 2 "plus_si_operand" "r,I,La,Le,Lb")))]
- "TARGET_64BIT"
+ ""
{
- if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])
- && ADDU16I_OPERAND (INTVAL (operands[2])))
- {
- rtx t1 = gen_reg_rtx (DImode);
- rtx t2 = gen_reg_rtx (DImode);
- rtx t3 = gen_reg_rtx (DImode);
- emit_insn (gen_extend_insn (t1, operands[1], DImode, SImode, 0));
- t2 = operands[2];
- emit_insn (gen_adddi3 (t3, t1, t2));
- t3 = gen_lowpart (SImode, t3);
- emit_move_insn (operands[0], t3);
- DONE;
- }
- else
+ if (TARGET_64BIT)
{
- rtx t = gen_reg_rtx (DImode);
- emit_insn (gen_addsi3_extended (t, operands[1], operands[2]));
- t = gen_lowpart (SImode, t);
- SUBREG_PROMOTED_VAR_P (t) = 1;
- SUBREG_PROMOTED_SET (t, SRP_SIGNED);
- emit_move_insn (operands[0], t);
- DONE;
+ if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])
+ && ADDU16I_OPERAND (INTVAL (operands[2])))
+ {
+ rtx t1 = gen_reg_rtx (DImode);
+ rtx t2 = gen_reg_rtx (DImode);
+ rtx t3 = gen_reg_rtx (DImode);
+ emit_insn (gen_extend_insn (t1, operands[1], DImode, SImode, 0));
+ t2 = operands[2];
+ emit_insn (gen_adddi3 (t3, t1, t2));
+ t3 = gen_lowpart (SImode, t3);
+ emit_move_insn (operands[0], t3);
+ DONE;
+ }
+ else
+ {
+ rtx t = gen_reg_rtx (DImode);
+ emit_insn (gen_addsi3_extended (t, operands[1], operands[2]));
+ t = gen_lowpart (SImode, t);
+ SUBREG_PROMOTED_VAR_P (t) = 1;
+ SUBREG_PROMOTED_SET (t, SRP_SIGNED);
+ emit_move_insn (operands[0], t);
+ DONE;
+ }
}
})
--
2.34.1
