Disable mlsx, mlasx, msimd, it may be support in future if necessary.
Extreme code model change to normal code model by default.
gcc/ChangeLog:
* config/loongarch/loongarch-opts.cc: Disable mlsx, mlasx, msimd,
extreme code mode on LA32
---
gcc/config/loongarch/loongarch-opts.cc | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/loongarch/loongarch-opts.cc
b/gcc/config/loongarch/loongarch-opts.cc
index fba06827c7b..17ee2b6a487 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -358,6 +358,12 @@ config_target_isa:
}
}
+ /* TARGET_32BIT and TARGET_64BIT init at the end of this function,
+ can't use here. */
+ if ((t.isa.base == ISA_BASE_LA32 || t.isa.base == ISA_BASE_LA32R)
+ && (t.isa.simd == ISA_EXT_SIMD_LSX || t.isa.simd == ISA_EXT_SIMD_LASX))
+ fatal_error (UNKNOWN_LOCATION, "SIMD is not supported on LA32");
+
/* All SIMD extensions imply a 64-bit FPU:
- silently adjust t.isa.fpu to "fpu64" if it is unconstrained.
- warn if -msingle-float / -msoft-float is on,
@@ -557,7 +563,15 @@ fallback:
case CMODEL_NORMAL:
case CMODEL_MEDIUM:
+ break;
+
case CMODEL_EXTREME:
+ if (t.isa.base == ISA_BASE_LA32 || t.isa.base == ISA_BASE_LA32R)
+ {
+ warning (0, "%qs is not supported, now cmodel is set to %qs",
+ loongarch_cmodel_strings[t.cmodel], "normal");
+ t.cmodel = CMODEL_NORMAL;
+ }
break;
default:
--
2.34.1
