Add TARGET_HARD_FLOAT condition for float instructions template.
Disable instructions that do not exist on la32r.
gcc/ChangeLog:
* config/loongarch/larchintrin.h (__movgr2fcsr): Disable on soft float.
(__crc_w_w_w): Disable on la32.
(__crc_w_d_w): Likewise.
(__crcc_w_w_w): Likewise.
(__iocsrrd_w): Likewise.
(__iocsrrd_d): Likewise.
(__iocsrwr_w): Likewise.
* config/loongarch/loongarch.cc (loongarch_legitimize_address): Disable
(plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) on la32r.
(loongarch_output_equal_conditional_branch): Disable beqz/bnez on la32r.
* config/loongarch/loongarch.md (!TARGET_32BIT_R): Disable rotatert.
(*and<mode>3): Delete and/andi, rename to *and<mode>3_extend.
(*and<mode>3_extend): New.
(zero_extend<SHORT:mode><GPR:mode>2_la32r): New.
(extend<SHORT:mode><GPR:mode>2_la32r): New.
(extendqihi2_la32r): New.
* config/loongarch/predicates.md: Disable low_bitmask_operand and
ins_zero_bitmask_operand on la32r.
* config/loongarch/sync.md: Change beqz to beq.
include/ChangeLog:
* longlong.h (count_leading_zeros): Delete on la32r.
(count_trailing_zeros): Likewise.
(COUNT_LEADING_ZEROS_0): Likewise.
---
gcc/config/loongarch/larchintrin.h | 18 +--
gcc/config/loongarch/loongarch.cc | 11 +-
gcc/config/loongarch/loongarch.md | 223 +++++++++++++++++------------
gcc/config/loongarch/predicates.md | 5 +-
gcc/config/loongarch/sync.md | 32 +++--
include/longlong.h | 6 +-
6 files changed, 169 insertions(+), 126 deletions(-)
diff --git a/gcc/config/loongarch/larchintrin.h
b/gcc/config/loongarch/larchintrin.h
index 299b1c6a49d..e0fe1df8c9c 100644
--- a/gcc/config/loongarch/larchintrin.h
+++ b/gcc/config/loongarch/larchintrin.h
@@ -80,6 +80,7 @@ __rdtimel_w (void)
return __rdtime;
}
+#ifdef __loongarch_hard_float
/* Assembly instruction format: rj, fcsr. */
/* Data types in instruction templates: USI, UQI. */
#define __movfcsr2gr(/*ui5*/ _1) __builtin_loongarch_movfcsr2gr ((_1));
@@ -88,13 +89,14 @@ __rdtimel_w (void)
/* Data types in instruction templates: VOID, UQI, USI. */
#define __movgr2fcsr(/*ui5*/ _1, _2) \
__builtin_loongarch_movgr2fcsr ((_1), _2);
+#endif
-#if defined __loongarch64
+#if __loongarch_grlen == 64
/* Assembly instruction format: ui5, rj, si12. */
/* Data types in instruction templates: VOID, USI, UDI, SI. */
#define __cacop_d(/*ui5*/ _1, /*unsigned long int*/ _2, /*si12*/ _3) \
__builtin_loongarch_cacop_d ((_1), (_2), (_3))
-#elif defined __loongarch32
+#elif __loongarch_grlen == 32
#define __cacop_w(/*ui5*/ _1, /*unsigned long int*/ _2, /*si12*/ _3) \
__builtin_loongarch_cacop_w ((_1), (_2), (_3))
#else
@@ -130,30 +132,31 @@ __asrtgt_d (long int _1, long int _2)
}
#endif
-#if defined __loongarch64
+#if __loongarch_grlen == 64
/* Assembly instruction format: rd, rj, ui5. */
/* Data types in instruction templates: DI, DI, UQI. */
#define __lddir_d(/*long int*/ _1, /*ui5*/ _2) \
__builtin_loongarch_lddir_d ((_1), (_2))
-#elif defined __loongarch32
+#elif __loongarch_grlen == 32
#define __lddir_w(/*long int*/ _1, /*ui5*/ _2) \
__builtin_loongarch_lddir_w ((_1), (_2))
#else
#error "Unsupported ABI."
#endif
-#if defined __loongarch64
+#if __loongarch_grlen == 64
/* Assembly instruction format: rj, ui5. */
/* Data types in instruction templates: VOID, DI, UQI. */
#define __ldpte_d(/*long int*/ _1, /*ui5*/ _2) \
__builtin_loongarch_ldpte_d ((_1), (_2))
-#elif defined __loongarch32
+#elif __loongarch_grlen == 32
#define __ldpte_w(/*long int*/ _1, /*ui5*/ _2) \
__builtin_loongarch_ldpte_w ((_1), (_2))
#else
#error "Unsupported ABI."
#endif
+#ifdef __loongarch64
/* Assembly instruction format: rd, rj, rk. */
/* Data types in instruction templates: SI, QI, SI. */
extern __inline int
@@ -181,7 +184,6 @@ __crc_w_w_w (int _1, int _2)
return __builtin_loongarch_crc_w_w_w (_1, _2);
}
-#ifdef __loongarch64
/* Assembly instruction format: rd, rj, rk. */
/* Data types in instruction templates: SI, DI, SI. */
extern __inline int
@@ -190,7 +192,6 @@ __crc_w_d_w (long int _1, int _2)
{
return __builtin_loongarch_crc_w_d_w (_1, _2);
}
-#endif
/* Assembly instruction format: rd, rj, rk. */
/* Data types in instruction templates: SI, QI, SI. */
@@ -219,7 +220,6 @@ __crcc_w_w_w (int _1, int _2)
return __builtin_loongarch_crcc_w_w_w (_1, _2);
}
-#ifdef __loongarch64
/* Assembly instruction format: rd, rj, rk. */
/* Data types in instruction templates: SI, DI, SI. */
extern __inline int
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 3607d429372..125e888aa58 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -3393,7 +3393,9 @@ loongarch_legitimize_address (rtx x, rtx oldx
ATTRIBUTE_UNUSED,
if (offset != 0)
{
/* Handle (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case.
*/
- if (GET_CODE (base) == PLUS && mem_shadd_or_shadd_rtx_p (XEXP (base, 0))
+ if ((TARGET_64BIT || TARGET_32BIT_S)
+ && GET_CODE (base) == PLUS
+ && mem_shadd_or_shadd_rtx_p (XEXP (base, 0))
&& IMM12_OPERAND (offset))
{
rtx index = XEXP (base, 0);
@@ -7554,7 +7556,8 @@ loongarch_output_equal_conditional_branch (rtx_insn
*insn, rtx *operands,
bool inverted_p)
{
const char *branch[2];
- if (operands[3] == const0_rtx)
+ if ((TARGET_64BIT || TARGET_32BIT_S)
+ && operands[3] == const0_rtx)
{
branch[!inverted_p] = LARCH_BRANCH ("b%C1z", "%2,%0");
branch[inverted_p] = LARCH_BRANCH ("b%N1z", "%2,%0");
@@ -8222,11 +8225,11 @@ loongarch_trampoline_init (rtx m_tramp, tree fndecl,
rtx chain_value)
/* Build up the code in TRAMPOLINE. */
i = 0;
- /*pcaddi $static_chain,0
+ /*pcaddu12i $static_chain,0
ld.[dw] $tmp,$static_chain,target_function_offset
ld.[dw] $static_chain,$static_chain,static_chain_offset
jirl $r0,$tmp,0 */
- trampoline[i++] = OP (0x18000000 | (STATIC_CHAIN_REGNUM - GP_REG_FIRST));
+ trampoline[i++] = OP (0x1c000000 | (STATIC_CHAIN_REGNUM - GP_REG_FIRST));
trampoline[i++] = OP ((ptr_mode == DImode ? 0x28c00000 : 0x28800000)
| 19 /* $t7 */
| ((STATIC_CHAIN_REGNUM - GP_REG_FIRST) << 5)
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 3c2096e91e7..c20f5724ba2 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -638,7 +638,7 @@ (define_int_attr bytepick_imm [(8 "1")
;; so the redundant sign extension can be removed if the output is used as
;; an input of a bitwise operation. Note plus, rotl, and div are handled
;; separately.
-(define_code_iterator shift_w [any_shift rotatert])
+(define_code_iterator shift_w [any_shift (rotatert "!TARGET_32BIT_R")])
(define_code_iterator arith_w [minus mult])
(define_expand "<optab><mode>3"
@@ -715,7 +715,7 @@ (define_insn "add<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fadd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -840,7 +840,7 @@ (define_insn "sub<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fsub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -877,7 +877,7 @@ (define_insn "mul<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fmul.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "<MODE>")])
@@ -1030,7 +1030,7 @@ (define_insn "*div<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fdiv.<fmt>\t%0,%1,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "<UNITMODE>")])
@@ -1041,7 +1041,7 @@ (define_insn "*recip<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"frecip.<fmt>\t%0,%2"
[(set_attr "type" "frdiv")
(set_attr "mode" "<UNITMODE>")])
@@ -1052,7 +1052,7 @@ (define_insn "loongarch_frecipe_<fmt>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_RECIPE))]
- "ISA_HAS_FRECIPE"
+ "TARGET_HARD_FLOAT && ISA_HAS_FRECIPE"
"frecipe.<fmt>\t%0,%1"
[(set_attr "type" "frecipe")
(set_attr "mode" "<UNITMODE>")
@@ -1156,7 +1156,7 @@ (define_insn "fma<mode>4"
(fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1167,7 +1167,7 @@ (define_insn "fms<mode>4"
(fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
- ""
+ "TARGET_HARD_FLOAT"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1184,7 +1184,7 @@ (define_insn "fnma<mode>4"
(fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
(match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f")))]
- "!HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1202,7 +1202,7 @@ (define_insn "fnms<mode>4"
(neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
(match_operand:ANYF 2 "register_operand" "f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
- "!HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1285,7 +1285,7 @@ (define_expand "sqrt<mode>2"
(define_insn "*sqrt<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fsqrt.<fmt>\t%0,%1"
[(set_attr "type" "fsqrt")
(set_attr "mode" "<UNITMODE>")
@@ -1295,7 +1295,7 @@ (define_expand "rsqrt<mode>2"
[(set (match_operand:ANYF 0 "register_operand")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand")]
UNSPEC_RSQRT))]
- "TARGET_HARD_FLOAT"
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
{
if (<MODE>mode == SFmode && TARGET_RECIP_RSQRT)
{
@@ -1319,7 +1319,7 @@ (define_insn "loongarch_frsqrte_<fmt>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_RSQRTE))]
- "ISA_HAS_FRECIPE"
+ "TARGET_HARD_FLOAT && ISA_HAS_FRECIPE"
"frsqrte.<fmt>\t%0,%1"
[(set_attr "type" "frsqrte")
(set_attr "mode" "<UNITMODE>")])
@@ -1334,7 +1334,7 @@ (define_insn "loongarch_frsqrte_<fmt>"
(define_insn "abs<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fabs.<fmt>\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "<UNITMODE>")])
@@ -1384,7 +1384,7 @@ (define_insn "ldexp<mode>3"
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
(match_operand:<IMODE> 2 "register_operand" "f")]
UNSPEC_FSCALEB))]
- "TARGET_HARD_FLOAT"
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
"fscaleb.<fmt>\t%0,%1,%2"
[(set_attr "type" "fscaleb")
(set_attr "mode" "<UNITMODE>")])
@@ -1400,7 +1400,7 @@ (define_insn "logb_non_negative<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_FLOGB))]
- "TARGET_HARD_FLOAT"
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
"flogb.<fmt>\t%0,%1"
[(set_attr "type" "flogb")
(set_attr "mode" "<UNITMODE>")])
@@ -1409,7 +1409,7 @@ (define_expand "logb<mode>2"
[(set (match_operand:ANYF 0 "register_operand")
(unspec:ANYF [(abs:ANYF (match_operand:ANYF 1 "register_operand"))]
UNSPEC_FLOGB))]
- "TARGET_HARD_FLOAT"
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
@@ -1429,7 +1429,7 @@ (define_expand "logb<mode>2"
(define_insn "clz<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=r")
(clz:GPR (match_operand:GPR 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"clz.<d>\t%0,%1"
[(set_attr "type" "clz")
(set_attr "mode" "<MODE>")])
@@ -1445,7 +1445,7 @@ (define_insn "clz<mode>2"
(define_insn "ctz<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=r")
(ctz:GPR (match_operand:GPR 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"ctz.<d>\t%0,%1"
[(set_attr "type" "clz")
(set_attr "mode" "<MODE>")])
@@ -1461,7 +1461,7 @@ (define_insn "smax<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smax:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_DOUBLE_FLOAT"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<MODE>")])
@@ -1470,7 +1470,7 @@ (define_insn "smin<mode>3"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smin:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<MODE>")])
@@ -1480,7 +1480,7 @@ (define_insn "fmax<mode>3"
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" "f"))
(use (match_operand:ANYF 2 "register_operand" "f"))]
UNSPEC_FMAX))]
- ""
+ "TARGET_HARD_FLOAT"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<MODE>")])
@@ -1490,7 +1490,7 @@ (define_insn "fmin<mode>3"
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" "f"))
(use (match_operand:ANYF 2 "register_operand" "f"))]
UNSPEC_FMIN))]
- ""
+ "TARGET_HARD_FLOAT"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<MODE>")])
@@ -1502,7 +1502,7 @@ (define_insn "smaxa<mode>3"
(abs:ANYF (match_operand:ANYF 2 "register_operand" "f")))
(match_dup 1)
(match_dup 2)))]
- ""
+ "TARGET_HARD_FLOAT"
"fmaxa.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<MODE>")])
@@ -1514,7 +1514,7 @@ (define_insn "smina<mode>3"
(abs:ANYF (match_operand:ANYF 2 "register_operand" "f")))
(match_dup 1)
(match_dup 2)))]
- ""
+ "TARGET_DOUBLE_FLOAT"
"fmina.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<MODE>")])
@@ -1545,7 +1545,7 @@ (define_insn "*negsi2_extended"
(define_insn "neg<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "TARGET_DOUBLE_FLOAT"
"fneg.<fmt>\t%0,%1"
[(set_attr "type" "fneg")
(set_attr "mode" "<UNITMODE>")])
@@ -1561,28 +1561,26 @@ (define_insn "neg<mode>2"
(define_insn "*<optab><mode>3"
[(set (match_operand:GPR 0 "register_operand" "=r,r")
- (any_or:GPR (match_operand:GPR 1 "register_operand" "%r,r")
- (match_operand:GPR 2 "uns_arith_operand" "r,K")))]
+ (any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r")
+ (match_operand:GPR 2 "uns_arith_operand" "r,K")))]
""
"<insn>%i2\t%0,%1,%2"
[(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
-(define_insn "*and<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r")
- (and:GPR (match_operand:GPR 1 "register_operand" "%r,r,r,0")
- (match_operand:GPR 2 "and_operand" "r,K,Yx,Yy")))]
- ""
+(define_insn "*and<mode>3_extend"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (and:GPR (match_operand:GPR 1 "register_operand" "%r,0")
+ (match_operand:GPR 2 "and_operand" "Yx,Yy")))]
+ "TARGET_64BIT || TARGET_32BIT_S"
"@
- and\t%0,%1,%2
- andi\t%0,%1,%2
* operands[2] = GEN_INT (INTVAL (operands[2]) \
& GET_MODE_MASK (<MODE>mode)); \
return \"bstrpick.<d>\t%0,%1,%M2\";
* operands[2] = GEN_INT (~INTVAL (operands[2]) \
& GET_MODE_MASK (<MODE>mode)); \
return \"bstrins.<d>\t%0,%.,%M2\";"
- [(set_attr "move_type" "logical,logical,pick_ins,pick_ins")
+ [(set_attr "move_type" "pick_ins,pick_ins")
(set_attr "mode" "<MODE>")])
(define_expand "<optab><mode>3"
@@ -1614,7 +1612,8 @@ (define_insn_and_split "*bstrins_<mode>_for_ior_mask"
(match_operand:GPR 2 "const_int_operand" "i"))
(and:GPR (match_operand:GPR 3 "register_operand" "r")
(match_operand:GPR 4 "const_int_operand" "i"))))]
- "loongarch_pre_reload_split ()
+ "(TARGET_64BIT || TARGET_32BIT_S )
+ && loongarch_pre_reload_split ()
&& loongarch_use_bstrins_for_ior_with_mask (<MODE>mode, operands)"
"#"
"&& true"
@@ -1668,7 +1667,7 @@ (define_peephole2
(match_operand:SI 3 "const_int_operand")
(const_int 0))
(match_dup 0))]
- "peep2_reg_dead_p (3, operands[0])"
+ "(TARGET_64BIT || TARGET_32BIT_S) && peep2_reg_dead_p (3, operands[0])"
[(const_int 0)]
{
int len = GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[3]);
@@ -1711,7 +1710,7 @@ (define_insn "<optab>n<mode>3"
(neg_bitwise:X
(not:X (match_operand:X 2 "register_operand" "r"))
(match_operand:X 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"<insn>n\t%0,%1,%2"
[(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
@@ -1808,7 +1807,7 @@ (define_insn "zero_extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=r,r,r")
(zero_extend:GPR
(match_operand:SHORT 1 "nonimmediate_operand" "r,m,k")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"@
bstrpick.w\t%0,%1,<SHORT:7_or_15>,0
ld.<SHORT:size>u\t%0,%1
@@ -1816,6 +1815,15 @@ (define_insn "zero_extend<SHORT:mode><GPR:mode>2"
[(set_attr "move_type" "pick_ins,load,load")
(set_attr "mode" "<GPR:MODE>")])
+(define_insn "zero_extend<SHORT:mode><GPR:mode>2_la32r"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (zero_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "m")))]
+ "TARGET_32BIT_R"
+ "ld.<SHORT:size>u\t%0,%1"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "<GPR:MODE>")])
+
(define_insn "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,k,m")))]
@@ -1833,7 +1841,7 @@ (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(zero_extend:GPR
(truncate:SHORT (match_operand:DI 1 "register_operand" "r"))))]
- "TARGET_64BIT"
+ "TARGET_64BIT || TARGET_32BIT_S"
"bstrpick.w\t%0,%1,<SHORT:7_or_15>,0"
[(set_attr "move_type" "pick_ins")
(set_attr "mode" "<GPR:MODE>")])
@@ -1842,7 +1850,7 @@ (define_insn "*zero_extendhi_truncqi"
[(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI
(truncate:QI (match_operand:DI 1 "register_operand" "r"))))]
- "TARGET_64BIT"
+ ""
"andi\t%0,%1,0xff"
[(set_attr "alu_type" "and")
(set_attr "mode" "HI")])
@@ -1872,7 +1880,7 @@ (define_insn "extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=r,r,r")
(sign_extend:GPR
(match_operand:SHORT 1 "nonimmediate_operand" "r,m,k")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"@
ext.w.<SHORT:size>\t%0,%1
ld.<SHORT:size>\t%0,%1
@@ -1880,6 +1888,15 @@ (define_insn "extend<SHORT:mode><GPR:mode>2"
[(set_attr "move_type" "signext,load,load")
(set_attr "mode" "<GPR:MODE>")])
+(define_insn "extend<SHORT:mode><GPR:mode>2_la32r"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (sign_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "m")))]
+ "TARGET_32BIT_R"
+ "ld.<SHORT:size>\t%0,%1"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "<GPR:MODE>")])
+
(define_insn "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
(sign_extend:HI
@@ -1892,6 +1909,15 @@ (define_insn "extendqihi2"
[(set_attr "move_type" "signext,load,load")
(set_attr "mode" "SI")])
+(define_insn "extendqihi2_la32r"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "m")))]
+ ""
+ "ld.b\t%0,%1"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "SI")])
+
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
@@ -1913,7 +1939,7 @@ (define_insn "extendsfdf2"
(define_insn "fix_trunc<ANYF:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=f")
(fix:GPR (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "TARGET_DOUBLE_FLOAT"
"ftintrz.<GPR:ifmt>.<ANYF:fmt> %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1932,7 +1958,7 @@ (define_insn "floatsidf2"
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(float:DF (match_operand:DI 1 "register_operand" "f")))]
- "TARGET_DOUBLE_FLOAT"
+ "(TARGET_64BIT || TARGET_32BIT_S) && TARGET_DOUBLE_FLOAT"
"ffint.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
@@ -2132,11 +2158,11 @@ (define_expand "fixuns_truncsfdi2"
;; ....................
(define_expand "extzv<mode>"
- [(set (match_operand:X 0 "register_operand")
- (zero_extract:X (match_operand:X 1 "register_operand")
+ [(set (match_operand:GPR 0 "register_operand")
+ (zero_extract:GPR (match_operand:GPR 1 "register_operand")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
{
if (!loongarch_use_ins_ext_p (operands[1], INTVAL (operands[2]),
INTVAL (operands[3])))
@@ -2144,12 +2170,13 @@ (define_expand "extzv<mode>"
})
(define_insn "*extzv<mode>"
- [(set (match_operand:X 0 "register_operand" "=r")
- (zero_extract:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")
- (match_operand 3 "const_int_operand" "")))]
- "loongarch_use_ins_ext_p (operands[1], INTVAL (operands[2]),
- INTVAL (operands[3]))"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "(TARGET_64BIT || TARGET_32BIT_S)
+ && loongarch_use_ins_ext_p (operands[1], INTVAL (operands[2]),
+ INTVAL (operands[3]))"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
return "bstrpick.<d>\t%0,%1,%2,%3";
@@ -2162,7 +2189,7 @@ (define_expand "insv<mode>"
(match_operand 1 "const_int_operand")
(match_operand 2 "const_int_operand"))
(match_operand:GPR 3 "reg_or_0_operand"))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
{
if (!loongarch_use_ins_ext_p (operands[0], INTVAL (operands[1]),
INTVAL (operands[2])))
@@ -2174,8 +2201,9 @@ (define_insn "*insv<mode>"
(match_operand:SI 1 "const_int_operand" "")
(match_operand:SI 2 "const_int_operand" ""))
(match_operand:GPR 3 "reg_or_0_operand" "rJ"))]
- "loongarch_use_ins_ext_p (operands[0], INTVAL (operands[1]),
- INTVAL (operands[2]))"
+ "(TARGET_64BIT || TARGET_32BIT_S)
+ && loongarch_use_ins_ext_p (operands[0], INTVAL (operands[1]),
+ INTVAL (operands[2]))"
{
operands[1] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]) - 1);
return "bstrins.<d>\t%0,%z3,%1,%2";
@@ -2296,7 +2324,7 @@ (define_insn "la_pcrel64_two_parts"
(unspec:DI [(match_operand:DI 2 "") (pc)] UNSPEC_LA_PCREL_64_PART1))
(set (match_operand:DI 1 "register_operand" "=r")
(unspec:DI [(match_dup 2) (pc)] UNSPEC_LA_PCREL_64_PART2))]
- "TARGET_ABI_LP64 && la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE"
+ "TARGET_64BIT && la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE"
{
return "pcalau12i\t%0,%r2\n\t"
"addi.d\t%1,$r0,%L2\n\t"
@@ -2416,7 +2444,7 @@ (define_insn "*movqi_internal"
(define_expand "movsf"
[(set (match_operand:SF 0 "")
(match_operand:SF 1 ""))]
- ""
+ "TARGET_HARD_FLOAT"
{
if (loongarch_legitimize_move (SFmode, operands[0], operands[1]))
DONE;
@@ -2447,7 +2475,7 @@ (define_insn "*movsf_softfloat"
(define_expand "movdf"
[(set (match_operand:DF 0 "")
(match_operand:DF 1 ""))]
- ""
+ "TARGET_DOUBLE_FLOAT"
{
if (loongarch_legitimize_move (DFmode, operands[0], operands[1]))
DONE;
@@ -2484,7 +2512,7 @@ (define_insn "*movdf_softfloat"
(define_expand "move_doubleword_2_<mode>"
[(set (match_operand:SPLITF 0)
(match_operand:SPLITF 1))]
- ""
+ "TARGET_HARD_FLOAT"
{
if (FP_REG_RTX_P (operands[0]))
{
@@ -2587,8 +2615,9 @@ (define_insn "*sel<code><GPR:mode>_using_<X:mode>"
(const_int 0))
(match_operand:GPR 2 "reg_or_0_operand" "r,J")
(match_operand:GPR 3 "reg_or_0_operand" "J,r")))]
- "register_operand (operands[2], <GPR:MODE>mode)
- != register_operand (operands[3], <GPR:MODE>mode)"
+ "(TARGET_64BIT || TARGET_32BIT_S)
+ && register_operand (operands[2], <GPR:MODE>mode)
+ != register_operand (operands[3], <GPR:MODE>mode)"
"@
<sel>\t%0,%2,%1
<selinv>\t%0,%3,%1"
@@ -2638,7 +2667,7 @@ (define_insn "*sel<mode>"
(const_int 0))
(match_operand:ANYF 2 "reg_or_0_operand" "f")
(match_operand:ANYF 3 "reg_or_0_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fsel\t%0,%3,%2,%1"
[(set_attr "type" "condmove")
(set_attr "mode" "<ANYF:MODE>")])
@@ -2650,7 +2679,7 @@ (define_expand "mov<mode>cc"
(if_then_else:GPR (match_operator 1 "comparison_operator"
[(match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "reg_or_0_operand")])))]
- "TARGET_COND_MOVE_INT"
+ "(TARGET_64BIT || TARGET_32BIT_S) && TARGET_COND_MOVE_INT"
{
if (!INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
FAIL;
@@ -2755,7 +2784,7 @@ (define_insn "@pcalau12i<mode>"
[(set (match_operand:P 0 "register_operand" "=j")
(unspec:P [(match_operand:P 1 "symbolic_operand" "")]
UNSPEC_PCALAU12I))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"pcalau12i\t%0,%%pc_hi20(%1)"
[(set_attr "type" "move")])
@@ -2765,7 +2794,7 @@ (define_insn "@pcalau12i_gr<mode>"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:P 1 "symbolic_operand" "")]
UNSPEC_PCALAU12I_GR))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"pcalau12i\t%0,%%pc_hi20(%1)"
[(set_attr "type" "move")])
@@ -2815,7 +2844,7 @@ (define_insn "rint<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_FRINT))]
- ""
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
"frint.<fmt>\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<MODE>")])
@@ -3136,7 +3165,7 @@ (define_insn "loongarch_lddir_<d>"
(match_operand 2 "const_uimm5_operand")]
UNSPECV_LDDIR)
(clobber (mem:BLK (scratch)))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"lddir\t%0,%1,%2"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")])
@@ -3146,7 +3175,7 @@ (define_insn "loongarch_ldpte_<d>"
(match_operand 1 "const_uimm5_operand")]
UNSPECV_LDPTE)
(clobber (mem:BLK (scratch)))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"ldpte\t%0,%1"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")])
@@ -3224,7 +3253,7 @@ (define_insn "*rotr<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=r,r")
(rotatert:GPR (match_operand:GPR 1 "register_operand" "r,r")
(match_operand:SI 2 "arith_operand" "r,I")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"rotr%i2.<d>\t%0,%1,%2"
[(set_attr "type" "shift,shift")
(set_attr "mode" "<MODE>")])
@@ -3234,7 +3263,7 @@ (define_insn "rotrsi3_extend"
(sign_extend:DI
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "arith_operand" "r,I"))))]
- "TARGET_64BIT"
+ "TARGET_64BIT || TARGET_32BIT_S"
"rotr%i2.w\t%0,%1,%2"
[(set_attr "type" "shift,shift")
(set_attr "mode" "SI")])
@@ -3246,7 +3275,7 @@ (define_expand "rotl<mode>3"
(set (match_operand:GPR 0 "register_operand")
(rotatert:GPR (match_operand:GPR 1 "register_operand")
(match_dup 3)))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
{
operands[3] = gen_reg_rtx (SImode);
@@ -3269,7 +3298,7 @@ (define_insn "alsl<mode>3"
(plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "r")
(match_operand 2 "const_immalsl_operand" ""))
(match_operand:GPR 3 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"alsl.<d>\t%0,%1,%3,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
@@ -3312,7 +3341,8 @@ (define_insn_and_split "<optab>_shift_reverse<X:mode>"
(ashift:X (match_operand:X 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:X 3 "const_int_operand" "i")))]
- "(const_immalsl_operand (operands[2], SImode)
+ "TARGET_64BIT
+ && (const_immalsl_operand (operands[2], SImode)
|| !<bitwise_operand> (operands[3], <MODE>mode))
&& loongarch_reassoc_shift_bitwise (<is_and>, operands[2], operands[3],
<MODE>mode)"
@@ -3394,7 +3424,7 @@ (define_insn "revb_2h"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (bswap:SI (match_operand:SI 1 "register_operand" "r"))
(const_int 16)))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"revb.2h\t%0,%1"
[(set_attr "type" "shift")])
@@ -3404,14 +3434,14 @@ (define_insn "revb_2h_extend"
(rotatert:SI
(bswap:SI (match_operand:SI 1 "register_operand" "r"))
(const_int 16))))]
- "TARGET_64BIT"
+ "TARGET_64BIT || TARGET_32BIT_S"
"revb.2h\t%0,%1"
[(set_attr "type" "shift")])
(define_insn "bswaphi2"
[(set (match_operand:HI 0 "register_operand" "=r")
(bswap:HI (match_operand:HI 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"revb.2h\t%0,%1"
[(set_attr "type" "shift")])
@@ -3433,9 +3463,9 @@ (define_insn "*bswapsi2"
(define_expand "bswapsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
{
- if (!TARGET_64BIT)
+ if (TARGET_32BIT_S)
{
rtx t = gen_reg_rtx (SImode);
emit_insn (gen_revb_2h (t, operands[1]));
@@ -3599,7 +3629,7 @@ (define_expand "cstore<mode>4"
(match_operator:SI 1 "loongarch_cstore_operator"
[(match_operand:GPR 2 "register_operand")
(match_operand:GPR 3 "nonmemory_operand")]))]
- ""
+ "TARGET_64BIT"
{
loongarch_expand_scc (operands);
DONE;
@@ -3666,7 +3696,7 @@ (define_insn "s<code>_<ANYF:mode>_using_FCCmode"
[(set (match_operand:FCC 0 "register_operand" "=z")
(fcond:FCC (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")))]
- ""
+ "TARGET_HARD_FLOAT"
"fcmp.<fcond>.<fmt>\t%Z0%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FCC")])
@@ -4418,7 +4448,7 @@ (define_insn "*bytepick_w_<bytepick_imm>"
(const_int <bytepick_w_lshiftrt_amount>))
(ashift:SI (match_operand:SI 2 "register_operand" "r")
(const_int bytepick_w_ashift_amount))))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"bytepick.w\t%0,%1,%2,<bytepick_imm>"
[(set_attr "mode" "SI")])
@@ -4436,7 +4466,7 @@ (define_insn "bytepick_w_<bytepick_imm>_extend"
(zero_extract:DI (match_operand:DI 2 "register_operand" "r")
(const_int <bytepick_w_ashift_amount>)
(const_int <bitsize>))))]
- "TARGET_64BIT"
+ "TARGET_64BIT || TARGET_32BIT_S"
"bytepick.w\t%0,%2,%1,<bytepick_imm>"
[(set_attr "mode" "SI")])
@@ -4451,7 +4481,7 @@ (define_insn "bytepick_w_1_extend"
(zero_extract:DI (match_operand:DI 2 "register_operand" "r")
(const_int 8)
(const_int 24))))]
- "TARGET_64BIT"
+ "TARGET_64BIT || TARGET_32BIT_S"
"bytepick.w\t%0,%2,%1,1"
[(set_attr "mode" "SI")])
@@ -4481,7 +4511,7 @@ (define_insn "bitrev_4b"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_BITREV_4B))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"bitrev.4b\t%0,%1"
[(set_attr "type" "unknown")
(set_attr "mode" "SI")])
@@ -4490,7 +4520,7 @@ (define_insn "bitrev_8b"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")]
UNSPEC_BITREV_8B))]
- ""
+ "TARGET_64BIT"
"bitrev.8b\t%0,%1"
[(set_attr "type" "unknown")
(set_attr "mode" "DI")])
@@ -4498,7 +4528,7 @@ (define_insn "bitrev_8b"
(define_insn "@rbit<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(bitreverse:GPR (match_operand:GPR 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"bitrev.<size>\t%0,%1"
[(set_attr "type" "unknown")
(set_attr "mode" "<MODE>")])
@@ -4517,7 +4547,7 @@ (define_insn "rbitsi_extended"
(define_insn "rbitqi"
[(set (match_operand:QI 0 "register_operand" "=r")
(bitreverse:QI (match_operand:QI 1 "register_operand" "r")))]
- ""
+ "TARGET_64BIT || TARGET_32BIT_S"
"bitrev.4b\t%0,%1"
[(set_attr "type" "unknown")
(set_attr "mode" "SI")])
@@ -4660,7 +4690,7 @@ (define_insn "loongarch_<crc>_w_<size>_w"
(unspec:SI [(match_operand:QHWD 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
CRC))]
- ""
+ "TARGET_64BIT"
"<crc>.w.<size>.w\t%0,%1,%2"
[(set_attr "type" "unknown")
(set_attr "mode" "<MODE>")])
@@ -4681,7 +4711,7 @@ (define_expand "crc_rev<mode>si4"
(match_operand:SI 1 "register_operand") ; old_chksum
(match_operand:SUBDI 2 "reg_or_0_operand") ; msg
(match_operand 3 "const_int_operand")] ; poly
- ""
+ "TARGET_64BIT"
{
unsigned HOST_WIDE_INT poly = UINTVAL (operands[3]);
rtx msg = operands[2];
@@ -4778,7 +4808,8 @@ (define_insn_and_split "*crc_combine"
(define_insn_and_rewrite "simple_load<mode>"
[(set (match_operand:LD_AT_LEAST_32_BIT 0 "register_operand" "=r,f")
(match_operand:LD_AT_LEAST_32_BIT 1 "mem_simple_ldst_operand" ""))]
- "loongarch_pre_reload_split ()
+ "(TARGET_64BIT || TARGET_32BIT_S)
+ && loongarch_pre_reload_split ()
&& la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)"
"#"
@@ -4791,7 +4822,8 @@ (define_insn_and_rewrite
"simple_load_<su>ext<SUBDI:mode><GPR:mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(any_extend:GPR
(match_operand:SUBDI 1 "mem_simple_ldst_operand" "")))]
- "loongarch_pre_reload_split ()
+ "(TARGET_64BIT || TARGET_32BIT_S)
+ && loongarch_pre_reload_split ()
&& la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)"
"#"
@@ -4803,7 +4835,8 @@ (define_insn_and_rewrite
"simple_load_<su>ext<SUBDI:mode><GPR:mode>"
(define_insn_and_rewrite "simple_store<mode>"
[(set (match_operand:ST_ANY 0 "mem_simple_ldst_operand" "")
(match_operand:ST_ANY 1 "reg_or_0_operand" "r,f"))]
- "loongarch_pre_reload_split ()
+ "(TARGET_64BIT || TARGET_32BIT_S)
+ && loongarch_pre_reload_split ()
&& la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)"
"#"
diff --git a/gcc/config/loongarch/predicates.md
b/gcc/config/loongarch/predicates.md
index 34cf74d5d66..dd30eb84c4e 100644
--- a/gcc/config/loongarch/predicates.md
+++ b/gcc/config/loongarch/predicates.md
@@ -291,7 +291,8 @@ (define_predicate "si_mask_operand"
(define_predicate "low_bitmask_operand"
(and (match_code "const_int")
- (match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
+ (match_test "low_bitmask_len (mode, INTVAL (op)) > 12")
+ (match_test "!TARGET_32BIT_R")))
(define_predicate "d_operand"
(and (match_code "reg")
@@ -400,8 +401,10 @@ (define_predicate "fcc_reload_operand"
(define_predicate "muldiv_target_operand"
(match_operand 0 "register_operand"))
+;;???
(define_predicate "ins_zero_bitmask_operand"
(and (match_code "const_int")
+ (match_test "!TARGET_32BIT_R")
(match_test "low_bitmask_len (mode, \
~UINTVAL (op) | (~UINTVAL(op) - 1)) \
> 0")
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index dcece77ea2e..92bdcf2bd75 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -254,7 +254,7 @@ (define_insn "atomic_storeti_scq"
UNSPEC_ATOMIC_STORE))
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_64BIT && ISA_HAS_SCQ"
- "1:\\n\\tll.d\t$r0,%0\n\tmove\t%2,%1\n\tsc.q\t%2,%t1,%0\n\tbeqz\t%2,1b"
+ "1:\\n\\tll.d\t$r0,%0\n\tmove\t%2,%1\n\tsc.q\t%2,%t1,%0\n\tbeq\t%2,$zero,1b"
[(set (attr "length") (const_int 16))])
(define_expand "atomic_storeti"
@@ -395,13 +395,21 @@ (define_insn "atomic_fetch_nand_mask_inverted<mode>"
(match_operand:GPR 2 "register_operand" "r"))]
UNSPEC_SYNC_OLD_OP))
(clobber (match_scratch:GPR 3 "=&r"))]
- "TARGET_64BIT || TARGET_32BIT_S"
+ ""
{
- return "1:\\n\\t"
- "ll.<d>\\t%0,%1\\n\\t"
- "orn\\t%3,%2,%0\\n\\t"
- "sc.<d>\\t%3,%1\\n\\t"
- "beqz\\t%3,1b";
+ if (TARGET_32BIT_R)
+ return "1:\\n\\t"
+ "ll.<d>\\t%0,%1\\n\\t"
+ "nor\\t%3,%0,$zero\\n\\t"
+ "or\\t%3,%2,%3\\n\\t"
+ "sc.<d>\\t%3,%1\\n\\t"
+ "beq\\t%3,$zero,1b";
+ else
+ return "1:\\n\\t"
+ "ll.<d>\\t%0,%1\\n\\t"
+ "orn\\t%3,%2,%0\\n\\t"
+ "sc.<d>\\t%3,%1\\n\\t"
+ "beq\\t%3,$zero,1b";
}
[(set (attr "length") (const_int 16))])
@@ -495,7 +503,7 @@ (define_insn "atomic_exchangeti_scq"
output_asm_insn ("ld.d\t%t0,%b1,8", operands);
output_asm_insn ("move\t%3,%z2", operands);
output_asm_insn ("sc.q\t%3,%t2,%1", operands);
- output_asm_insn ("beqz\t%3,1b", operands);
+ output_asm_insn ("beq\t%3,$zero,1b", operands);
return "";
}
@@ -558,7 +566,7 @@ (define_insn "atomic_cas_value_strong<mode>"
output_asm_insn ("or%i3\t%5,$zero,%3", operands);
output_asm_insn ("sc.<size>\t%5,%1", operands);
- output_asm_insn ("beqz\t%5,1b", operands);
+ output_asm_insn ("beq\t%5,$zero,1b", operands);
output_asm_insn ("%T4b\t3f", operands);
output_asm_insn ("2:", operands);
output_asm_insn ("%G4", operands);
@@ -844,7 +852,7 @@ (define_insn "atomic_compare_and_swapti_scq"
output_asm_insn ("sc.q\t%7,%t3,%1", operands);
/* Check if sc.q has done the store. */
- output_asm_insn ("beqz\t%7,1b", operands);
+ output_asm_insn ("beq\t%7,$zero,1b", operands);
/* Jump over the mod_f barrier if sc.q has succeeded. */
output_asm_insn ("%T4b\t3f", operands);
@@ -998,7 +1006,7 @@ (define_insn "atomic_cas_value_exchange_7_<mode>"
"and\\t%7,%0,%z3\\n\\t"
"or%i5\\t%7,%7,%5\\n\\t"
"sc.<size>\\t%7,%1\\n\\t"
- "beqz\\t%7,1b\\n\\t";
+ "beq\\t%7,$zero,1b\\n\\t";
}
[(set (attr "length") (const_int 20))])
@@ -1095,7 +1103,7 @@ (define_insn "atomic_fetch_<amop_ti_fetch>ti_scq"
}
output_asm_insn ("sc.q\t%3,%4,%1", operands);
- output_asm_insn ("beqz\t%3,1b", operands);
+ output_asm_insn ("beq\t%3,$zero,1b", operands);
return "";
}
diff --git a/include/longlong.h b/include/longlong.h
index 5ae250f7192..9429e90e0d1 100644
--- a/include/longlong.h
+++ b/include/longlong.h
@@ -594,11 +594,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
#endif
#ifdef __loongarch__
-# if W_TYPE_SIZE == 32
-# define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
-# define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
-# define COUNT_LEADING_ZEROS_0 32
-# elif W_TYPE_SIZE == 64
+# if W_TYPE_SIZE == 64
# define count_leading_zeros(count, x) ((count) = __builtin_clzll (x))
# define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x))
# define COUNT_LEADING_ZEROS_0 64
--
2.34.1
