This patch is a minor modification of my previous patch that was necessary when I changed how -mcpu=future was supported. This patch requires at least the -mcpu=future patch to be installed. It would be nice if the 2nd patch in the -mcpu=future patchset was installed also before these patches are installed:
* https://gcc.gnu.org/pipermail/gcc-patches/2025-November/700539.html * https://gcc.gnu.org/pipermail/gcc-patches/2025-November/700540.html I've had these patches floating around since 2023 that add support for a potential extension to the PowerPC called the dense math facility. The Dense Math Facility (dmf) is designed to be an extension to the ISA 3.1 (i.e. power10/power11) MMA facility. Now, since these are future patches, the Dense Math Facility might appear in future PowerPC machines or maybe it won't be used in real hardware. One of the concepts of the DMF system is the accumulators used in the MMA and the DMF extensions will become separate registers, rather than being overlaid over the traditional floating point registers (i.e. VSX registers 0..31). In addition to being separate registers, the dense math accumulators are now logically 1,024 biits instead of 512. The way the Dense Math registers and instructions are designed, existing power10/power11 MMA instructions that operate on 512 bits will work with Dense Math. In ISA 3.1, each of the 8 accumulators are overlaid over 4 adjacent FPR registers, and the compiler must not touch the 4 adjacent FPRs while the MMA accumulator is used. In the Dense Math system, the accumulator is a separate register. When -mcpu=power11 or -mcpu=power10 is used, the GCC compiler will not allocate the appropriate FPR (VSX) reigsters when generating MMA instructions. If a function compiled for Power10/Power11 is run on a system with Dense Math support enabled, the effect is a bunch of the FPR registers will not be allocated because the compiler assumes the accumulaters are there. After these patches are applied, if the user compiles the code with -mcpu=future, the compiler can allocate up to 32 more vector registers, because the Dense Math accumulators are separate registers. In fact two of the MMA tests (mma-double-test.c and mma-single-test.c) do about 20 less spills of floating point values to the stack, since the compiler can allocate those FPR vector registers for other purposes. These 3 patches will allow GCC to allocate these registers if the -mcpu=future option is used. 1: The first patch adds a new constraint (%wD) that can be used by code generating MMA instructions. If the user used -mcpu=power10 or -mcpu=power11, %wD will act like %d and insist the register be VSX registers 0..31. If the user used -mcpu=future, the new separate dense math accumulators will be used. 2: This patch adds the support for the current MMA 512-bit instructions to use separate accumulators instead of overlaid VSX registers. 3: This patch adds support for an extension to MMA where the accumulators grow to 1,024 bits instead of 512 bits. This patch is the foundation for the Dense Math support. It is expected other patches may be added to this to support potential new features added to the Dense Math Facility. I have built bootstrap little endian compilers on power10 systems, and there were no regression in the tests. Can I add the patches to the GCC trunk after the -mcpu=future patch is applied? -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
