So one of Andrew's patches recently triggered numerous scan failures on the RISC-V port. It's our friends the vsetvl tests.
Andrew's change slightly alters the branching structure of the code and that causes many of the vsetvl tests to go nuts since they require a specific set of instructions/lables in a particular order -- even though the tests are really about testing the vsetvl insertion & optimization phase of the compiler.
Rather than continue to fix up what we concluded a year or two ago was a bad idea, this just rips out the non-essential matching bits. It leaves the vsetvl testing in place (as one would expect).
I didn't do the whole vsetvl subdirectory, just those tests which were causing problems. I'm inclined to fault in more fixes as we need them.
Pushing to the trunk. jeff
commit 332d8340dff3f3975530908fbd114bbf82b9ccba Author: Jeff Law <[email protected]> Date: Fri Nov 14 14:46:32 2025 -0700 [RISC-V] Drop scan-tests of marginal value gcc/testsuite * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Drop unnecessary output test(s). * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Likewise. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Likewise. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c index 9bade063f17e..d3d0c5a70332 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c @@ -26,4 +26,3 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[0-9]00\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[0-9]00\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[0-9]00\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c index 723a1c6c9fcb..7bbd802fa3d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c index f2dab3ada558..efa6216f2e98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c index 94fb31fcfc65..459b3f048d2d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c index 1805bcd32203..7cad98461a3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c index 68d0af739139..ada64d973c70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c index 89c785ec4719..a7b40e69f5b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c @@ -214,4 +214,3 @@ void f7 (void * restrict in, void * restrict out, int n, int cond) /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c index af4ba3cc0a7b..2439c5e270ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c index a081dda8b370..3f30b151db31 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c index e27c76c9f188..9492510802c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c index 16c8fd9e0e95..00b5ac355f1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c index af0df897290c..7f7c520ebad9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c index 69c642340b69..d5c74af9e43e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c index 78d8e9de00ca..2d93e2832c53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c index 993e420a87b5..ce187afb3c06 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c index d1547c9c106b..d79be09baa57 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c index 836619f93da2..6d2cf5b30fab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c index e61bb9cc1639..b2e1d8826b7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c index b4b4c66059c1..af8f7623d938 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c index 0910b0cdabd8..f47a332d8362 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c index 661e5c0c23cc..fc9e8d52c5e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c @@ -37,4 +37,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c index 8cbbfaba8d09..8f91736a8743 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c @@ -234,4 +234,3 @@ void f7 (void * restrict in, void * restrict out, int n, int cond) /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*v[0-9]+,0\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c index 10df345c441a..82a40c81194c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c index fb7197a0a780..9069fc5525b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c index 66833743627c..e736e1c66670 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c index 7066d77e53ab..1b09a23a1257 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c index 452890090ba4..1f75a6ab4037 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c index 4d1acf9d9a58..00aba0ac843b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c index 5bfc6593e9b5..59feeef4e041 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c @@ -34,4 +34,3 @@ void f (void * restrict in, void * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ -/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
