> -----Original Message-----
> From: Jakub Jelinek <[email protected]>
> Sent: Friday, November 21, 2025 2:26 PM
> To: Liu, Hongtao <[email protected]>; Uros Bizjak <[email protected]>
> Cc: [email protected]
> Subject: [PATCH] i386: Remove cond_{ashl,lshr,ashr}v{64,16,32}qi expanders
> [PR122598]
>
> Hi!
>
> As mentioned in the PR, the COND_SH{L,R} internal fns are expanded without
> fallback, their expansion must succeed, and furthermore they don't
> differentiate between scalar and vector shift counts, so again both have to be
> supported. That is the case of the {ashl,lshr,ashr}v*[hsd]i patterns which
> use
> nonimmediate_or_const_vec_dup_operand predicate for the shift count, so if
> the argument isn't const vec dup, it can be always legitimized by loading
> into a
> vector register.
> This is not the case of the QImode element conditional vector shifts, there is
> no fallback for those and we emit individual element shifts in that case when
> not conditional and shift count is not a constant.
>
> So, I'm afraid we can't announce such an expander because then the
> vectorizer etc. count with it being fully available.
>
> As I've tried to show in
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122598#c9
> even without this pattern we can sometimes emit
> vgf2p8affineqb $0, .LC0(%rip), %ymm0, %ymm0{%k1}
> etc. instructions.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
Ok.
>
> 2025-11-20 Jakub Jelinek <[email protected]>
>
> PR target/122598
> * config/i386/predicates.md (const_vec_dup_operand): Remove.
> * config/i386/sse.md (cond<<insn><mode> with VI1_AVX512VL
> iterator):
> Remove.
>
> * gcc.target/i386/pr122598.c: New test.
>
> --- gcc/config/i386/predicates.md.jj 2025-09-16 19:24:23.095153913
> +0200
> +++ gcc/config/i386/predicates.md 2025-11-20 14:08:02.699932716
> +0100
> @@ -1319,9 +1319,6 @@ (define_predicate "nonimmediate_or_const
> (ior (match_operand 0 "nonimmediate_operand")
> (match_test "const_vec_duplicate_p (op)")))
>
> -(define_predicate "const_vec_dup_operand"
> - (match_test "const_vec_duplicate_p (op)"))
> -
> ;; Return true when OP is either register operand, or any ;; CONST_VECTOR.
> (define_predicate "reg_or_const_vector_operand"
> --- gcc/config/i386/sse.md.jj 2025-11-18 09:57:19.361169021 +0100
> +++ gcc/config/i386/sse.md 2025-11-20 14:08:26.074605116 +0100
> @@ -27293,24 +27293,6 @@ (define_expand "<insn><mode>3"
> DONE;
> })
>
> -(define_expand "cond_<insn><mode>"
> - [(set (match_operand:VI1_AVX512VL 0 "register_operand")
> - (vec_merge:VI1_AVX512VL
> - (any_shift:VI1_AVX512VL
> - (match_operand:VI1_AVX512VL 2 "register_operand")
> - (match_operand:VI1_AVX512VL 3 "const_vec_dup_operand"))
> - (match_operand:VI1_AVX512VL 4 "nonimm_or_0_operand")
> - (match_operand:<avx512fmaskmode> 1 "register_operand")))]
> - "TARGET_GFNI && TARGET_AVX512F"
> -{
> - rtx count = XVECEXP (operands[3], 0, 0);
> - rtx matrix = ix86_vgf2p8affine_shift_matrix (operands[0], count, <CODE>);
> - emit_insn (gen_vgf2p8affineqb_<mode>_mask (operands[0], operands[2],
> matrix,
> - const0_rtx, operands[4],
> - operands[1]));
> - DONE;
> -})
> -
> (define_expand "<insn><mode>3"
> [(set (match_operand:VI1_AVX512_3264 0 "register_operand")
> (any_rotate:VI1_AVX512_3264
> --- gcc/testsuite/gcc.target/i386/pr122598.c.jj 2025-11-20
> 14:18:50.893537789 +0100
> +++ gcc/testsuite/gcc.target/i386/pr122598.c 2025-11-20
> 14:19:09.845261048 +0100
> @@ -0,0 +1,14 @@
> +/* PR target/122598 */
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mavx512f -mgfni" } */
> +
> +typedef char V __attribute__ ((vector_size (64)));
> +
> +V
> +foo (V v)
> +{
> + v >>= (V) {5};
> + v -= ~0;
> + v += (V) {} < v;
> + return v;
> +}
>
> Jakub
