Hi, As discussed, we need to relax the requirement on __vector_pair and __vector_quad so that it is not tied up to MMA.
In this patch, I have tried to relax it to the power isa 3.0, since it has load and store vector instructions in DQ-form, which is needed in case where we split the mov insn into multiple load/store after register allocation. But in case, if we want to relax it further so that it works with power isa v2.06 using the indexed form loads/stores(lxvd2x/stxvd2x), I am not sure how to split it before the register allocation, since the hard reg numbers are actually required to do the split. Kindly review. Please let me know if this solution is ok or there are other ways on how to achieve the split before register allocation. Thanks and regards, Avinash Jayakar This patch relaxes the requirement on the types '__vector_pair' and '__vector_quad' which previously required the -mmma option to be used. In power9/powerpc isa 3.0, there are instructions in DQ form that could be used to load and store a pair of vector registers namely lxv and stxv, which can be used to implement the mov insns for the OOmode(pair) and XOmode(quad). In order to split the OOmode into 2 128bit registers and load/store them separately, it is necessary to have this happen after register allocation. But since no new registers can be allocated after that the index form of load/stores (lxvd2x/stxvd2x) cannot be used in this phase. Updated the tests for pr106736 and 108272, which were both expecting these types not to be supported on power9. I have split them to 2 variants, one for power9, where pair and quad type produces 2 and 4 load/store insns respectively. Another for power8, which should emit error message without ICE. 2025-11-25 Avinash Jayakar <[email protected]> PR 106736 PR 108272 gcc/ChangeLog: * config/rs6000/mma.md (*movoo_p10): Seperate out OOmode moves for TARGET_MMA. (*movoo): Relax to TARGET_P9_VECTOR and use rs6000_split_multireg_move function for splitting. (*movxo): Relax to TARGET_P9_VECTOR. (movoo): Likewise. (movxo): Likewise. * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): OOmode can be used with TARGET_P9_VECTOR. (rs6000_split_multireg_move): Handle moves in OOmode with TARGET_MMA. (rs6000_opaque_type_invalid_use_p): Update error messages for __vector_pair and __vector_quad usage. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr106736-1.c: Move to... * gcc.target/powerpc/pr106736-p9-1.c: ...here. * gcc.target/powerpc/pr106736-2.c: Move to... * gcc.target/powerpc/pr106736-p9-2.c: ...here. * gcc.target/powerpc/pr106736-3.c: Move to... * gcc.target/powerpc/pr106736-p9-3.c: ...here. * gcc.target/powerpc/pr106736-4.c: Move to... * gcc.target/powerpc/pr106736-p9-4.c: ...here. * gcc.target/powerpc/pr106736-5.c: Move to... * gcc.target/powerpc/pr106736-p9-5.c: ...here. * gcc.target/powerpc/pr108272-1.c: Move to... * gcc.target/powerpc/pr108272-p8-1.c: ...here. * gcc.target/powerpc/pr108272-2.c: Move to... * gcc.target/powerpc/pr108272-p8-2.c: ...here. * gcc.target/powerpc/pr108272-3.c: Move to... * gcc.target/powerpc/pr108272-p8-3.c: ...here. * gcc.target/powerpc/pr108272-4.c: Move to... * gcc.target/powerpc/pr108272-p8-4.c: ...here. * gcc.target/powerpc/pr106736-p8-1.c: New test. * gcc.target/powerpc/pr106736-p8-2.c: New test. * gcc.target/powerpc/pr106736-p8-3.c: New test. * gcc.target/powerpc/pr106736-p8-4.c: New test. * gcc.target/powerpc/pr106736-p8-5.c: New test. * gcc.target/powerpc/pr108272-p9-1.c: New test. * gcc.target/powerpc/pr108272-p9-2.c: New test. * gcc.target/powerpc/pr108272-p9-3.c: New test. * gcc.target/powerpc/pr108272-p9-4.c: New test. --- gcc/config/rs6000/mma.md | 26 +++++++++++++------ gcc/config/rs6000/rs6000.cc | 14 +++++----- .../gcc.target/powerpc/pr106736-p8-1.c | 18 +++++++++++++ .../gcc.target/powerpc/pr106736-p8-2.c | 15 +++++++++++ .../gcc.target/powerpc/pr106736-p8-3.c | 16 ++++++++++++ .../gcc.target/powerpc/pr106736-p8-4.c | 17 ++++++++++++ .../gcc.target/powerpc/pr106736-p8-5.c | 16 ++++++++++++ .../powerpc/{pr106736-1.c => pr106736-p9-1.c} | 3 ++- .../powerpc/{pr106736-2.c => pr106736-p9-2.c} | 3 ++- .../powerpc/{pr106736-3.c => pr106736-p9-3.c} | 3 ++- .../powerpc/{pr106736-4.c => pr106736-p9-4.c} | 3 ++- .../powerpc/{pr106736-5.c => pr106736-p9-5.c} | 4 +-- .../powerpc/{pr108272-1.c => pr108272-p8-1.c} | 9 +++---- .../powerpc/{pr108272-2.c => pr108272-p8-2.c} | 9 +++---- .../powerpc/{pr108272-3.c => pr108272-p8-3.c} | 9 +++---- .../powerpc/{pr108272-4.c => pr108272-p8-4.c} | 9 +++---- .../gcc.target/powerpc/pr108272-p9-1.c | 13 ++++++++++ .../gcc.target/powerpc/pr108272-p9-2.c | 13 ++++++++++ .../gcc.target/powerpc/pr108272-p9-3.c | 13 ++++++++++ .../gcc.target/powerpc/pr108272-p9-4.c | 12 +++++++++ 20 files changed, 185 insertions(+), 40 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106736-p8-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106736-p8-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106736-p8-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106736-p8-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106736-p8-5.c rename gcc/testsuite/gcc.target/powerpc/{pr106736-1.c => pr106736-p9-1.c} (83%) rename gcc/testsuite/gcc.target/powerpc/{pr106736-2.c => pr106736-p9-2.c} (81%) rename gcc/testsuite/gcc.target/powerpc/{pr106736-3.c => pr106736-p9-3.c} (81%) rename gcc/testsuite/gcc.target/powerpc/{pr106736-4.c => pr106736-p9-4.c} (81%) rename gcc/testsuite/gcc.target/powerpc/{pr106736-5.c => pr106736-p9-5.c} (81%) rename gcc/testsuite/gcc.target/powerpc/{pr108272-1.c => pr108272-p8-1.c} (53%) rename gcc/testsuite/gcc.target/powerpc/{pr108272-2.c => pr108272-p8-2.c} (53%) rename gcc/testsuite/gcc.target/powerpc/{pr108272-3.c => pr108272-p8-3.c} (54%) rename gcc/testsuite/gcc.target/powerpc/{pr108272-4.c => pr108272-p8-4.c} (55%) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108272-p9-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108272-p9-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108272-p9-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108272-p9-4.c diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 85f3a926682..422c2744837 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -269,7 +269,7 @@ (match_operand:OO 1 "input_operand"))] "" { - if (TARGET_MMA) + if (TARGET_P9_VECTOR) { rs6000_emit_move (operands[0], operands[1], OOmode); DONE; @@ -291,18 +291,28 @@ gcc_assert (false); }) +(define_insn "*movoo_p10" + [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO") + (match_operand:OO 1 "input_operand" "ZwO,wa"))] + "TARGET_MMA + && (gpc_reg_operand (operands[0], OOmode) + || gpc_reg_operand (operands[1], OOmode))" + "@ + lxvp%X1 %x0,%1 + stxvp%X0 %x1,%0" + [(set_attr "type" "vecload,vecstore")]) + (define_insn_and_split "*movoo" [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa") (match_operand:OO 1 "input_operand" "ZwO,wa,wa"))] - "TARGET_MMA + "TARGET_P9_VECTOR && (gpc_reg_operand (operands[0], OOmode) || gpc_reg_operand (operands[1], OOmode))" "@ - lxvp%X1 %x0,%1 - stxvp%X0 %x1,%0 + # + # #" - "&& reload_completed - && (!MEM_P (operands[0]) && !MEM_P (operands[1]))" + "&& reload_completed" [(const_int 0)] { rs6000_split_multireg_move (operands[0], operands[1]); @@ -319,7 +329,7 @@ (match_operand:XO 1 "input_operand"))] "" { - if (TARGET_MMA) + if (TARGET_P9_VECTOR) { rs6000_emit_move (operands[0], operands[1], XOmode); DONE; @@ -341,7 +351,7 @@ (define_insn_and_split "*movxo" [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d") (match_operand:XO 1 "input_operand" "ZwO,d,d"))] - "TARGET_MMA + "TARGET_P9_VECTOR && (gpc_reg_operand (operands[0], XOmode) || gpc_reg_operand (operands[1], XOmode))" "@ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 1d5cd25c0f0..e51b4670a95 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1861,11 +1861,11 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) /* Vector pair modes need even/odd VSX register pairs. Only allow vector registers. */ if (mode == OOmode) - return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0); + return (TARGET_P9_VECTOR && VSX_REGNO_P (regno) && (regno & 1) == 0); /* MMA accumulator modes need FPR registers divisible by 4. */ if (mode == XOmode) - return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0); + return (TARGET_P9_VECTOR && FP_REGNO_P (regno) && (regno & 3) == 0); /* PTImode can only go in GPRs. Quad word memory operations require even/odd register combinations, and use PTImode where we need to deal with quad @@ -27403,7 +27403,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we have a vector quad register for MMA, and this is a load or store, see if we can use vector paired load/stores. */ - if (mode == XOmode && TARGET_MMA + if ((mode == XOmode || mode == OOmode) && TARGET_MMA && (MEM_P (dst) || MEM_P (src))) { reg_mode = OOmode; @@ -29301,7 +29301,7 @@ constant_generates_xxspltidp (vec_const_128bit_type *vsx_const) bool rs6000_opaque_type_invalid_use_p (gimple *stmt) { - if (TARGET_MMA) + if (TARGET_P9_VECTOR) return false; /* If the given TYPE is one MMA opaque type, emit the corresponding @@ -29311,12 +29311,14 @@ rs6000_opaque_type_invalid_use_p (gimple *stmt) tree mv = TYPE_MAIN_VARIANT (type); if (mv == vector_quad_type_node) { - error ("type %<__vector_quad%> requires the %qs option", "-mmma"); + error ("type %<__vector_quad%> is supported from power isa 3.0 which \ + is available is %qs and later.", "POWER9"); return true; } else if (mv == vector_pair_type_node) { - error ("type %<__vector_pair%> requires the %qs option", "-mmma"); + error ("type %<__vector_pair%> is supported from power isa 3.0 which \ + is available is %qs and later.", "POWER9"); return true; } return false; diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-p8-1.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-1.c new file mode 100644 index 00000000000..a5f0610c677 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-1.c @@ -0,0 +1,18 @@ +/* If the default cpu type is power9 or later, type __vector_quad is + supported. To keep the test point available all the time, this case + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ + +/* Verify there is no ICE and don't check the error messages on unsupported + type since they could be fragile and are not test points of this case. */ + +/* { dg-excess-errors "pr106736-p8-1" } */ + +extern void bar (__vector_quad *); + +void +foo (__vector_quad *a, __vector_quad *b) +{ + __vector_quad arr[2] = {*a, *b}; + bar (&arr[0]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-p8-2.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-2.c new file mode 100644 index 00000000000..c0b1d96a0cf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-2.c @@ -0,0 +1,15 @@ +/* If the default cpu type is power9 or later, type __vector_pair is + supported. To keep the test point available all the time, this case + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ + +/* Verify there is no ICE and don't check the error messages on unsupported + type since they could be fragile and are not test points of this case. */ + +/* { dg-excess-errors "pr106736-p8-2" } */ + +void +foo (__vector_pair *a, __vector_pair *b) +{ + *a = *b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-p8-3.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-3.c new file mode 100644 index 00000000000..f90dab267e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-3.c @@ -0,0 +1,16 @@ +/* If the default cpu type is power9 or later, type __vector_quad is + supported. To keep the test point available all the time, this case + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ + +/* Verify there is no ICE and don't check the error messages on unsupported + type since they could be fragile and are not test points of this case. */ + +/* { dg-excess-errors "pr106736-p8-3" } */ + +__vector_quad ga; +void +foo (__vector_quad *a) +{ + ga = *a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-p8-4.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-4.c new file mode 100644 index 00000000000..6326036e87b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-4.c @@ -0,0 +1,17 @@ +/* If the default cpu type is power9 or later, type __vector_quad is + supported. To keep the test point available all the time, this case + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ + +/* Verify there is no ICE and don't check the error messages on unsupported + type since they could be fragile and are not test points of this case. */ + +/* { dg-excess-errors "pr106736-p8-4" } */ + +__vector_quad ga; +__vector_quad gb; +void +foo () +{ + gb = ga; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-p8-5.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-5.c new file mode 100644 index 00000000000..8d9655c9bf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p8-5.c @@ -0,0 +1,16 @@ +/* If the default cpu type is power9 or later, type __vector_pair is + supported. To keep the test point available all the time, this case + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ + +/* Verify there is no ICE and don't check the error messages on unsupported + type since they could be fragile and are not test points of this case. */ + +/* { dg-excess-errors "pr106736-p8-5" } */ + +__vector_pair ga; +void +foo (__vector_pair *a) +{ + *a = ga; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-1.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-1.c similarity index 83% rename from gcc/testsuite/gcc.target/powerpc/pr106736-1.c rename to gcc/testsuite/gcc.target/powerpc/pr106736-p9-1.c index 65bd79d3dce..2f00c15e15f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106736-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-1.c @@ -7,7 +7,6 @@ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr106736-1" } */ extern void bar (__vector_quad *); @@ -18,3 +17,5 @@ foo (__vector_quad *a, __vector_quad *b) bar (&arr[0]); } +/* { dg-final { scan-assembler-times {\mlxv\M} 8 } } */ +/* { dg-final { scan-assembler-times {\mstxv\M} 8 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-2.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-2.c similarity index 81% rename from gcc/testsuite/gcc.target/powerpc/pr106736-2.c rename to gcc/testsuite/gcc.target/powerpc/pr106736-p9-2.c index 12ad936fccc..7c4ac690e6f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106736-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-2.c @@ -7,7 +7,6 @@ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr106736-2" } */ void foo (__vector_pair *a, __vector_pair *b) @@ -15,3 +14,5 @@ foo (__vector_pair *a, __vector_pair *b) *a = *b; } +/* { dg-final { scan-assembler-times {\mlxv\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxv\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-3.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-3.c similarity index 81% rename from gcc/testsuite/gcc.target/powerpc/pr106736-3.c rename to gcc/testsuite/gcc.target/powerpc/pr106736-p9-3.c index 4fb368b8fb5..fc33f7d6e19 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106736-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-3.c @@ -7,7 +7,6 @@ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr106736-3" } */ __vector_quad ga; void @@ -16,3 +15,5 @@ foo (__vector_quad *a) ga = *a; } +/* { dg-final { scan-assembler-times {\mlxv\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-4.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-4.c similarity index 81% rename from gcc/testsuite/gcc.target/powerpc/pr106736-4.c rename to gcc/testsuite/gcc.target/powerpc/pr106736-p9-4.c index 4b366416b0a..96ddadaaf37 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106736-4.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-4.c @@ -7,7 +7,6 @@ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr106736-4" } */ __vector_quad ga; __vector_quad gb; @@ -17,3 +16,5 @@ foo () gb = ga; } +/* { dg-final { scan-assembler-times {\mlxv\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106736-5.c b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-5.c similarity index 81% rename from gcc/testsuite/gcc.target/powerpc/pr106736-5.c rename to gcc/testsuite/gcc.target/powerpc/pr106736-p9-5.c index d7370b81e81..b245f9b1d7a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106736-5.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106736-p9-5.c @@ -7,8 +7,6 @@ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr106736-5" } */ - __vector_pair ga; void foo (__vector_pair *a) @@ -16,3 +14,5 @@ foo (__vector_pair *a) *a = ga; } +/* { dg-final { scan-assembler-times {\mlxv\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxv\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-1.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-1.c similarity index 53% rename from gcc/testsuite/gcc.target/powerpc/pr108272-1.c rename to gcc/testsuite/gcc.target/powerpc/pr108272-p8-1.c index b99e6a4d86d..2f0860928ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr108272-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-1.c @@ -1,13 +1,12 @@ -/* { dg-require-effective-target powerpc_p9modulo_ok } */ -/* If the default cpu type is power10 or later, type __vector_quad is +/* If the default cpu type is power9 or later, type __vector_quad is supported. To keep the test point available all the time, this case - specifies -mdejagnu-cpu=power9 here. */ -/* { dg-options "-mdejagnu-cpu=power9" } */ + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr108272-1" } */ +/* { dg-excess-errors "pr108272-p8-1" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-2.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-2.c similarity index 53% rename from gcc/testsuite/gcc.target/powerpc/pr108272-2.c rename to gcc/testsuite/gcc.target/powerpc/pr108272-p8-2.c index 51b2100d0f1..5994d0c1c05 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr108272-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-2.c @@ -1,13 +1,12 @@ -/* { dg-require-effective-target powerpc_p9modulo_ok } */ -/* If the default cpu type is power10 or later, type __vector_pair is +/* If the default cpu type is power9 or later, type __vector_pair is supported. To keep the test point available all the time, this case - specifies -mdejagnu-cpu=power9 here. */ -/* { dg-options "-mdejagnu-cpu=power9" } */ + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr108272-2" } */ +/* { dg-excess-errors "pr108272-p8-2" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-3.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-3.c similarity index 54% rename from gcc/testsuite/gcc.target/powerpc/pr108272-3.c rename to gcc/testsuite/gcc.target/powerpc/pr108272-p8-3.c index 634a529b5c8..bd589ad7184 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr108272-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-3.c @@ -1,13 +1,12 @@ -/* { dg-require-effective-target powerpc_p9modulo_ok } */ -/* If the default cpu type is power10 or later, type __vector_quad is +/* If the default cpu type is power9 or later, type __vector_quad is supported. To keep the test point available all the time, this case - specifies -mdejagnu-cpu=power9 here. */ -/* { dg-options "-mdejagnu-cpu=power9" } */ + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr108272-3" } */ +/* { dg-excess-errors "pr108272-p8-3" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-4.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-4.c similarity index 55% rename from gcc/testsuite/gcc.target/powerpc/pr108272-4.c rename to gcc/testsuite/gcc.target/powerpc/pr108272-p8-4.c index 7eecd6c5a0d..685dd39e64c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr108272-4.c +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p8-4.c @@ -1,13 +1,12 @@ -/* { dg-require-effective-target powerpc_p9modulo_ok } */ -/* If the default cpu type is power10 or later, type __vector_pair is +/* If the default cpu type is power9 or later, type __vector_pair is supported. To keep the test point available all the time, this case - specifies -mdejagnu-cpu=power9 here. */ -/* { dg-options "-mdejagnu-cpu=power9" } */ + specifies -mdejagnu-cpu=power8 here. */ +/* { dg-options "-mdejagnu-cpu=power8" } */ /* Verify there is no ICE and don't check the error messages on unsupported type since they could be fragile and are not test points of this case. */ -/* { dg-excess-errors "pr108272-4" } */ +/* { dg-excess-errors "pr108272-p8-4" } */ typedef __vector_pair vpair_t; void diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-p9-1.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-1.c new file mode 100644 index 00000000000..4c72a9136af --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-1.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target powerpc_p9modulo_ok } */ +/* For power9, check if __vector_quad loads/stores are supported. */ +/* { dg-options "-mdejagnu-cpu=power9" } */ + + +void +foo (void) +{ + __vector_quad acc; + asm("#..." : "=d"(acc)); +} + +/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-p9-2.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-2.c new file mode 100644 index 00000000000..02632ba4276 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-2.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target powerpc_p9modulo_ok } */ +/* For power9, check if __vector_pair loads/stores are supported. */ +/* { dg-options "-mdejagnu-cpu=power9" } */ + + +void +foo (void) +{ + __vector_pair acc; + asm("#..." :: "d"(acc)); +} + +/* { dg-final { scan-assembler-times {\mlxv\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-p9-3.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-3.c new file mode 100644 index 00000000000..261960c3faa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-3.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target powerpc_p9modulo_ok } */ +/* For power9, check if __vector_quad loads/stores are supported. */ +/* { dg-options "-mdejagnu-cpu=power9" } */ + + +void +foo (void) +{ + __vector_quad acc; + asm("#..." :: "d"(acc)); +} + +/* { dg-final { scan-assembler-times {\mlxv\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr108272-p9-4.c b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-4.c new file mode 100644 index 00000000000..4cfb671da5a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr108272-p9-4.c @@ -0,0 +1,12 @@ +/* { dg-require-effective-target powerpc_p9modulo_ok } */ +/* For power9, check if __vector_pair loads/stores are supported. */ +/* { dg-options "-mdejagnu-cpu=power9" } */ + +typedef __vector_pair vpair_t; +void +foo (void) +{ + vpair_t acc; + asm("#..." : "=d"(acc)); +} +/* { dg-final { scan-assembler-times {\mstxv\M} 2 } } */ -- 2.47.3
