LGTM :)
On Wed, Nov 26, 2025 at 3:29 PM Kuan-Lin Chen <[email protected]> wrote: > The Andes 23 series is a 3-stage, in-order execution pipeline and > configurable dual-ALU execution. > > Co-author: Allen Bing-Sung Lu ([email protected]) > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-23-series. > (RISCV_CORE): Add Andes 23-series cpu list. > * config/riscv/riscv-opts.h > (enum riscv_microarchitecture_type): Add andes_23_series. > * config/riscv/riscv.cc: Add andes_23_tune_info. > * config/riscv/riscv.md: Add andes_23. > * doc/riscv-mcpu.texi: Regenerated for Andes cpu list. > * doc/riscv-mtune.texi: Regenerated for andes-23-series. > * config/riscv/andes-23-series.md: New file. > --- > gcc/config/riscv/andes-23-series.md | 190 ++++++++++++++++++++++++++++ > gcc/config/riscv/riscv-cores.def | 7 + > gcc/config/riscv/riscv-opts.h | 1 + > gcc/config/riscv/riscv.cc | 25 ++++ > gcc/config/riscv/riscv.md | 3 +- > gcc/doc/riscv-mcpu.texi | 4 + > gcc/doc/riscv-mtune.texi | 2 + > 7 files changed, 231 insertions(+), 1 deletion(-) > create mode 100644 gcc/config/riscv/andes-23-series.md > > diff --git a/gcc/config/riscv/andes-23-series.md > b/gcc/config/riscv/andes-23-series.md > new file mode 100644 > index 00000000000..8e19e05da17 > --- /dev/null > +++ b/gcc/config/riscv/andes-23-series.md > @@ -0,0 +1,190 @@ > +;; DFA-based pipeline description for Andes 23 series. > +;; > +;; Copyright (C) 2025 Free Software Foundation, Inc. > +;; > +;; This file is part of GCC. > +;; > +;; GCC is free software; you can redistribute it and/or modify it > +;; under the terms of the GNU General Public License as published > +;; by the Free Software Foundation; either version 3, or (at your > +;; option) any later version. > + > +;; GCC is distributed in the hope that it will be useful, but WITHOUT > +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > +;; License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; <http://www.gnu.org/licenses/>. > + > +(define_automaton "andes_23_arch") > + > +(define_cpu_unit > + "andes_23_alu0, andes_23_alu1, andes_23_lsu0, > + andes_23_lsu1, andes_23_lsu2" > + "andes_23_arch") > + > +(define_cpu_unit "andes_23_mdu" "andes_23_arch") > +(define_cpu_unit "andes_23_fpu" "andes_23_arch") > + > +;; andes 23 unsupported insns are mapped to dummies reservations > +(define_reservation "andes_23_dummies" > + "andes_23_alu0 | andes_23_alu1 | andes_23_lsu0 | andes_23_lsu1 | > + andes_23_lsu2 | andes_23_mdu | andes_23_fpu") > + > +(define_reservation "andes_23_alu" > + "andes_23_alu0 | andes_23_alu1") > + > +(define_reservation "andes_23_lsu" > + "andes_23_lsu0 | andes_23_lsu1 | andes_23_lsu2") > + > +(define_reservation "andes_23_pipe_unify" > + "andes_23_alu0 + andes_23_alu1") > + > +(define_insn_reservation "andes_23_alu_insn" 1 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "unknown,const,arith,slt,multi,nop,move, > + shift,logical,mvpair,auipc")) > + "andes_23_alu") > + > +(define_insn_reservation "andes_23_load" 3 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "load")) > + "andes_23_pipe_unify, andes_23_lsu*3") > + > +(define_insn_reservation "andes_23_store" 0 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "store")) > + "andes_23_pipe_unify,andes_23_lsu*3") > + > +(define_insn_reservation "andes_23_branch" 0 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) > + "andes_23_pipe_unify") > + > +(define_insn_reservation "andes_23_imul" 2 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "imul")) > + "andes_23_alu0, andes_23_mdu") > + > +(define_insn_reservation "andes_23_idivsi" 35 > + (and (eq_attr "tune" "andes_23_series") > + (and (eq_attr "type" "idiv") > + (eq_attr "mode" "SI"))) > + "andes_23_pipe_unify, andes_23_mdu* 34") > + > +(define_insn_reservation "andes_23_idivdi" 35 > + (and (eq_attr "tune" "andes_23_series") > + (and (eq_attr "type" "idiv") > + (eq_attr "mode" "DI"))) > + "andes_23_pipe_unify, andes_23_mdu* 34") > + > +(define_insn_reservation "andes_23_xfer" 1 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "mfc,mtc")) > + "andes_23_alu") > + > +(define_insn_reservation "andes_23_fpu_alu" 4 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fadd")) > + "andes_23_pipe_unify, andes_23_fpu") > + > +(define_insn_reservation "andes_23_fpu_mul" 4 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fmul")) > + "andes_23_pipe_unify, andes_23_fpu") > + > +(define_insn_reservation "andes_23_fpu_mac" 4 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fmadd")) > + "andes_23_pipe_unify, andes_23_fpu") > + > +(define_insn_reservation "andes_23_fpu_div" 33 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fdiv")) > + "andes_23_pipe_unify, andes_23_fpu*33") > + > +(define_insn_reservation "andes_23_fpu_sqrt" 33 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fsqrt")) > + "andes_23_pipe_unify, andes_23_fpu*33") > + > +(define_insn_reservation "andes_23_fpu_move" 2 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fmove,mtc,mfc")) > + "andes_23_pipe_unify, andes_23_fpu") > + > +(define_insn_reservation "andes_23_fpu_cmp" 3 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fcmp")) > + "andes_23_pipe_unify, andes_23_fpu") > + > +(define_insn_reservation "andes_23_fpu_cvt" 3 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i")) > + "andes_23_pipe_unify, andes_23_fpu") > + > +(define_insn_reservation "andes_23_fpu_load" 3 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fpload")) > + "andes_23_pipe_unify, andes_23_lsu*3") > + > +(define_insn_reservation "andes_23_fpu_store" 0 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "fpstore")) > + "andes_23_pipe_unify, andes_23_lsu*3") > + > +(define_insn_reservation "andes_23_bitmanip" 1 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" > "bitmanip,minu,maxu,min,max,clmul,rotate,cpop,clz,ctz")) > + "andes_23_alu0") > + > +(define_insn_reservation "andes_23_crypto" 1 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "crypto")) > + "andes_23_alu0") > + > +(define_bypass 3 > + "andes_23_fpu_mul" > + "andes_23_fpu_alu,andes_23_fpu_mac, > + andes_23_fpu_div,andes_23_fpu_sqrt") > + > +(define_bypass 3 > + "andes_23_fpu_alu" > + "andes_23_fpu_mul,andes_23_fpu_alu,andes_23_fpu_mac, > + andes_23_fpu_div,andes_23_fpu_sqrt") > + > +(define_bypass 3 > + "andes_23_fpu_mac" > + "andes_23_fpu_mul,andes_23_fpu_alu,andes_23_fpu_mac, > + andes_23_fpu_div,andes_23_fpu_sqrt") > + > +(define_bypass 2 > + "andes_23_fpu_load" > + "andes_23_fpu_div,andes_23_fpu_sqrt") > + > +(define_insn_reservation "andes_23_unknown" 1 > + (and (eq_attr "tune" "andes_23_series") > + (eq_attr "type" "ghost,zicond,mvpair,sfb_alu,condmove,atomic, > + vclz,vror,vsha2ch,vsm4k,vaesef,vghsh,vsm4r,vsm3c, > + > vaeskf1,vandn,vaesdm,vclmul,vclmulh,vrol,vcpop,vbrev8, > + vsm3me,vbrev,vctz,vgmul,vsha2ms,vaesz,vrev8, > + vaeskf2,vsha2cl,vwsll,vaesdf,vaesem,vfwmaccbf16, > + sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip,vmsfs,vfwalu, > + > vnshift,vldm,vslidedown,vicmp,vfcvtftoi,vmffs,vlsegdux, > + vfredo,vstux,vsshift,vfwcvtbf16,vmpop,vicalu,vldff, > + > vislide1down,vstox,vfwcvtftof,vfmov,vislide1up,vldr, > + > vfmul,vfrecp,vfncvtitof,vfwcvtftoi,vsts,viminmax,vext, > + > vaalu,vfdiv,vidiv,viwalu,vssegte,wrvxrm,vfmovvf,vlde, > + > vfclass,vshift,vimovxv,vssegtox,vfsqrt,vector,vmalu, > + vfcvtitof,vlsegdff,vfslide1down,vimov,vialu,vmidx, > + vsalu,vfmerge,rdvl,vlds,vfmuladd,vfsgnj,vslideup, > + > vfcmp,vfmovfv,vfwcvtitof,vfwmuladd,vfwredo,vlsegdox, > + > viwmul,vldox,vsmul,vstm,vfminmax,vmov,vfalu,vfncvtbf16, > + > vnclip,vimerge,vfwmul,vimovvx,vfncvtftoi,viwred,rdvlenb, > + > vfslide1up,vfncvtftof,vsetvl,viwmuladd,vfredu,vfwredu, > + > vlsegde,vmiota,vstr,vgather,vssegts,vldux,vlsegds,vimul, > + > vste,vsetvl_pre,vimuladd,vcompress,vssegtux,wrfrm,rdfrm, > + vired")) > + "andes_23_dummies") > diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > index abe9d496cda..e5f093e5819 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -55,6 +55,7 @@ RISCV_TUNE("generic-ooo", generic_ooo, > generic_ooo_tune_info) > RISCV_TUNE("size", generic, optimize_size_tune_info) > RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info) > RISCV_TUNE("andes-25-series", andes_25_series, andes_25_tune_info) > +RISCV_TUNE("andes-23-series", andes_23_series, andes_23_tune_info) > > #undef RISCV_TUNE > > @@ -181,6 +182,12 @@ RISCV_CORE("andes-nx25", > "rv64imc_zicsr_zifencei_xandesperf", "andes-25- > RISCV_CORE("andes-ax25", "rv64imafdc_zicsr_zifencei_xandesperf", > "andes-25-series") > RISCV_CORE("andes-a27", "rv32imafdc_zicsr_zifencei_xandesperf", > "andes-25-series") > RISCV_CORE("andes-ax27", "rv64imafdc_zicsr_zifencei_xandesperf", > "andes-25-series") > +RISCV_CORE("andes-n225", "rv32im_zicsr_zifencei_zca_zcb_zcmp_zcmt_" > + "zba_zbb_zbc_zbs_xandesperf", > + "andes-23-series") > +RISCV_CORE("andes-d23", > "rv32im_zicsr_zifencei_zicbop_zicbom_zicboz_" > + > "zca_zcb_zcmp_zcmt_zba_zbb_zbc_zbs_xandesperf", > + "andes-23-series") > RISCV_CORE("spacemit-x60", "rv64imafdcv_zba_zbb_zbc_zbs_zicboz_zicond_" > "zbkc_zfh_zvfh_zvkt_zvl256b_sscofpmf", > "spacemit-x60") > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index bca5382485c..c112b1da47c 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -61,6 +61,7 @@ enum riscv_microarchitecture_type { > generic_ooo, > mips_p8700, > tt_ascalon_d8, > + andes_23_series, > andes_25_series, > spacemit_x60, > }; > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 2d14b3c92f5..c3c4021c6a8 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -784,6 +784,31 @@ static const struct riscv_tune_param > spacemit_x60_tune_info= { > true, /* > prefer-agnostic. */ > }; > > +/* Costs to use when optimizing for Andes 23 series. */ > +static const struct riscv_tune_param andes_23_tune_info = { > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ > + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ > + {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* int_mul */ > + {COSTS_N_INSNS (24), COSTS_N_INSNS (24)}, /* int_div */ > + 2, /* issue_rate */ > + 3, /* branch_cost */ > + 3, /* memory_cost */ > + 8, /* fmv_cost */ > + false, /* slow_unaligned_access */ > + false, /* vector_unaligned_access > */ > + true, /* > use_divmod_expansion */ > + false, /* overlap_op_by_pieces */ > + false, /* use_zero_stride_load */ > + false, /* > speculative_sched_vsetvl */ > + RISCV_FUSE_NOTHING, /* fusible_ops */ > + NULL, /* vector cost */ > + NULL, /* function_align > */ > + NULL, /* jump_align */ > + NULL, /* loop_align */ > + true, /* > prefer-agnostic. */ > +}; > + > static bool riscv_avoid_shrink_wrapping_separate (); > static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool > *); > static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index affccec2b5e..aa4631e15a4 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -674,7 +674,7 @@ > ;; Keep this in sync with enum riscv_microarchitecture. > (define_attr "tune" > > "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700, > - tt_ascalon_d8,andes_25_series,spacemit_x60" > + tt_ascalon_d8,andes_25_series,andes_23_series,spacemit_x60" > (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) > > ;; Describe a user's asm statement. > @@ -4989,5 +4989,6 @@ > (include "generic-vector-ooo.md") > (include "generic-ooo.md") > (include "tt-ascalon-d8.md") > +(include "andes-23-series.md") > (include "andes-25-series.md") > (include "spacemit-x60.md") > diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi > index 8fcba597ad1..8875ff5bcb9 100644 > --- a/gcc/doc/riscv-mcpu.texi > +++ b/gcc/doc/riscv-mcpu.texi > @@ -82,4 +82,8 @@ by particular CPU name. Permissible values for this > option are: > > @samp{andes-ax27}, > > +@samp{andes-n225}, > + > +@samp{andes-d23}, > + > @samp{spacemit-x60}. > diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi > index 02fcd342384..578a641b2ba 100644 > --- a/gcc/doc/riscv-mtune.texi > +++ b/gcc/doc/riscv-mtune.texi > @@ -60,4 +60,6 @@ particular CPU name. Permissible values for this option > are: > > @samp{andes-25-series}, > > +@samp{andes-23-series}, > + > and all valid options for @option{-mcpu=}. > -- > 2.34.1 > >
