LGTM :) On Wed, Nov 26, 2025 at 3:38 PM Kuan-Lin Chen <[email protected]> wrote:
> The Andes 45 series is a 8-stage, in-order, and dual-issue execution > pipeline. > > Co-author: Allen Bing-Sung Lu ([email protected]) > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-45-sereis. > (RISCV_CORE): Add Andes 45 series cpu list. > * config/riscv/riscv-opts.h > (enum riscv_microarchitecture_type): Add andes_45_series. > * config/riscv/riscv.cc: Add andes_45_tune_info. > * config/riscv/riscv.md: Add andes_45. > * doc/riscv-mcpu.texi: Regenerated for Andes cpu list. > * doc/riscv-mtune.texi: Regenerated for andes-45-series. > * config/riscv/andes-45-series.md: New file. > --- > gcc/config/riscv/andes-45-series.md | 379 ++++++++++++++++++++++++++++ > gcc/config/riscv/riscv-cores.def | 6 + > gcc/config/riscv/riscv-opts.h | 1 + > gcc/config/riscv/riscv.cc | 25 ++ > gcc/config/riscv/riscv.md | 3 +- > gcc/doc/riscv-mcpu.texi | 8 + > gcc/doc/riscv-mtune.texi | 2 + > 7 files changed, 423 insertions(+), 1 deletion(-) > create mode 100644 gcc/config/riscv/andes-45-series.md > > diff --git a/gcc/config/riscv/andes-45-series.md > b/gcc/config/riscv/andes-45-series.md > new file mode 100644 > index 00000000000..7693db84746 > --- /dev/null > +++ b/gcc/config/riscv/andes-45-series.md > @@ -0,0 +1,379 @@ > +;; DFA-based pipeline description for Andes 45 series. > +;; > +;; Copyright (C) 2025 Free Software Foundation, Inc. > +;; > +;; This file is part of GCC. > +;; > +;; GCC is free software; you can redistribute it and/or modify it > +;; under the terms of the GNU General Public License as published > +;; by the Free Software Foundation; either version 3, or (at your > +;; option) any later version. > + > +;; GCC is distributed in the hope that it will be useful, but WITHOUT > +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > +;; License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; <http://www.gnu.org/licenses/>. > + > +(define_automaton "andes_45_arch, andes_45_vector") > + > +(define_cpu_unit "andes_45_pipe0" "andes_45_arch") > +(define_cpu_unit "andes_45_pipe1" "andes_45_arch") > +(define_cpu_unit "andes_45_vpu_pipe0" "andes_45_vector") > +(define_cpu_unit "andes_45_vpu_pipe1" "andes_45_vector") > + > +(define_reservation "andes_45_vpu_pipe" "(andes_45_vpu_pipe0 + > andes_45_pipe0 | andes_45_vpu_pipe1 + andes_45_pipe1)") > + > +(define_cpu_unit > "andes_45_mdu,andes_45_alu0,andes_45_alu1,andes_45_bru0,andes_45_bru1,andes_45_lsu" > "andes_45_arch") > +(define_cpu_unit > "andes_45_fpu_fmac,andes_45_fpu_fdiv,andes_45_fpu_fmis,andes_45_fpu_fmv" > "andes_45_arch") > +(define_cpu_unit > "andes_45_vpu_alu,andes_45_vpu_mac,andes_45_vpu_fmis,andes_45_vpu_permut, > + > andes_45_vpu_div,andes_45_vpu_fdiv,andes_45_vpu_mask,andes_45_vpu_lsu" > "andes_45_vector") > + > +(define_reservation "andes_45_fpu_arith" > + "andes_45_pipe0 + andes_45_fpu_fmac | andes_45_pipe1 + > andes_45_fpu_fmac") > + > +;; andes 45 series unsupported insns are mapped to dummies reservations > +(define_reservation "andes_45_dummies" > + "andes_45_pipe0 | andes_45_pipe1, andes_45_alu0 | andes_45_alu1") > + > +;; andes 45 series vector unsupported insns are mapped to dummies > reservations > +(define_reservation "andes_45_vector_dummies" > + "andes_45_pipe0 | andes_45_pipe1, andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_alu_insn_s" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "shift,nop,logical")) > + "andes_45_pipe0 + andes_45_alu0 | andes_45_pipe1 + andes_45_alu1") > + > +(define_insn_reservation "andes_45_alu_insn_l" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" > "unknown,const,arith,multi,slt,move,auipc,atomic,bitmanip")) > + "andes_45_pipe0 + andes_45_alu0 | andes_45_pipe1 + andes_45_alu1") > + > +(define_insn_reservation "andes_45_cmov" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "condmove")) > + "andes_45_pipe0 + andes_45_alu0 + andes_45_pipe1 + andes_45_alu1") > + > +(define_insn_reservation "andes_45_load_wd" 4 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "load") > + (not (eq_attr "mode" "QI,HI")))) > + "andes_45_pipe0 + andes_45_lsu | andes_45_pipe1 + andes_45_lsu") > + > +(define_insn_reservation "andes_45_load_bh" 5 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "load") > + (eq_attr "mode" "QI,HI"))) > + "andes_45_pipe0 + andes_45_lsu | andes_45_pipe1 + andes_45_lsu") > + > +(define_insn_reservation "andes_45_store_d" 0 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "store") > + (eq_attr "mode" "DI,SI"))) > + "andes_45_pipe0 + andes_45_lsu | andes_45_pipe1 + andes_45_lsu") > + > +(define_insn_reservation "andes_45_store" 0 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "store") > + (not (eq_attr "mode" "DI,SI")))) > + "andes_45_pipe0 + andes_45_pipe1 + andes_45_lsu") > + > +(define_insn_reservation "andes_45_branch" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "branch,jump,call,ret,jalr,trap")) > + "andes_45_pipe0 + andes_45_bru0 | andes_45_pipe1 + andes_45_bru1") > + > +(define_insn_reservation "andes_45_imul" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "imul")) > + "andes_45_pipe0 + andes_45_alu0 | andes_45_pipe1 + andes_45_alu1, > andes_45_mdu * 2") > + > +(define_insn_reservation "andes_45_idivsi" 38 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "idiv") > + (eq_attr "mode" "SI"))) > + "andes_45_pipe0 + andes_45_alu0 | andes_45_pipe1 + andes_45_alu1, > andes_45_mdu * 2") > + > +(define_insn_reservation "andes_45_idivdi" 70 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "idiv") > + (eq_attr "mode" "DI"))) > + "andes_45_pipe0 + andes_45_alu0 | andes_45_pipe1 + andes_45_alu1, > andes_45_mdu * 2") > + > +(define_insn_reservation "andes_45_xfer" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "mfc,mtc")) > + "andes_45_pipe0 + andes_45_alu0 | andes_45_pipe1 + andes_45_alu1") > + > +(define_insn_reservation "andes_45_fpu_alu_s" 3 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "fadd") > + (eq_attr "mode" "SF"))) > + "andes_45_fpu_arith") > + > +(define_insn_reservation "andes_45_fpu_alu_d" 4 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "fadd") > + (eq_attr "mode" "DF"))) > + "andes_45_fpu_arith") > + > +(define_insn_reservation "andes_45_fpu_mul_s" 3 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "fmul") > + (eq_attr "mode" "SF"))) > + "andes_45_fpu_arith") > + > +(define_insn_reservation "andes_45_fpu_mul_d" 4 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "fmul") > + (eq_attr "mode" "DF"))) > + "andes_45_fpu_arith") > + > +(define_insn_reservation "andes_45_fpu_mac_s" 3 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "fmadd") > + (eq_attr "mode" "SF"))) > + "(andes_45_pipe0 | andes_45_pipe1) + andes_45_fpu_fmac + > andes_45_fpu_fmv + andes_45_fpu_fmis") > + > +(define_insn_reservation "andes_45_fpu_mac_d" 4 > + (and (eq_attr "tune" "andes_45_series") > + (and (eq_attr "type" "fmadd") > + (eq_attr "mode" "DF"))) > + "(andes_45_pipe0 | andes_45_pipe1) + andes_45_fpu_fmac + > andes_45_fpu_fmv + andes_45_fpu_fmis") > + > +(define_insn_reservation "andes_45_fpu_div" 33 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fdiv")) > + "andes_45_pipe0 + andes_45_fpu_fdiv | andes_45_pipe1 + > andes_45_fpu_fdiv, andes_45_fpu_fdiv * 27") > + > +(define_insn_reservation "andes_45_fpu_sqrt" 33 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fsqrt")) > + "andes_45_pipe0 + andes_45_fpu_fdiv | andes_45_pipe1 + > andes_45_fpu_fdiv, andes_45_fpu_fdiv * 27") > + > +(define_insn_reservation "andes_45_fpu_move" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fmove,mtc,mfc")) > + "andes_45_pipe0 + andes_45_fpu_fmv | andes_45_pipe1 + andes_45_fpu_fmv") > + > +(define_insn_reservation "andes_45_fpu_cmp" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fcmp")) > + "andes_45_pipe0 + andes_45_fpu_fmis | andes_45_pipe1 + > andes_45_fpu_fmis") > + > +(define_insn_reservation "andes_45_fpu_cvt" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fcvt,fcvt_f2i,fcvt_i2f")) > + "andes_45_pipe0 + andes_45_fpu_fmis | andes_45_pipe1 + > andes_45_fpu_fmis") > + > +(define_insn_reservation "andes_45_fpu_load" 4 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fpload")) > + "andes_45_pipe0 + andes_45_pipe1 + andes_45_lsu") > + > +(define_insn_reservation "andes_45_fpu_store" 0 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "fpstore")) > + "andes_45_pipe0 + andes_45_pipe1 + andes_45_lsu") > + > +(define_insn_reservation "andes_45_vpu_load_e" 8 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vlde,vldm,vldr,vlsegde,vldff,vlsegdff")) > + "(andes_45_vpu_pipe + andes_45_vpu_lsu), andes_45_vpu_lsu * 2") > + > +(define_insn_reservation "andes_45_vpu_load_s" 10 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vlds,vlsegds")) > + "(andes_45_vpu_pipe + andes_45_vpu_lsu), andes_45_vpu_lsu * 3") > + > +(define_insn_reservation "andes_45_vpu_load_x" 12 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vldox,vldux,vlsegdox,vlsegdux")) > + "(andes_45_vpu_pipe + andes_45_vpu_lsu), andes_45_vpu_lsu * 4") > + > +(define_insn_reservation "andes_45_vpu_store" 0 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vste,vstm,vstr,vsts,vstux,vstox,vssegtox,vssegte, > + vssegtux,vssegts")) > + "andes_45_vpu_pipe + andes_45_lsu + andes_45_vpu_lsu") > + > +(define_insn_reservation "andes_45_vpu_alu" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vialu,viwalu,vicalu,vsalu,vaalu,vector")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_ext" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vext")) > + "andes_45_vpu_pipe + andes_45_vpu_permut") > + > +(define_insn_reservation "andes_45_vpu_shift" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vshift,vnshift,vsshift")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_minmax" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "viminmax")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_cmp" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vicmp")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_mul" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vimul,viwmul,vsmul")) > + "andes_45_vpu_pipe + andes_45_vpu_mac") > + > +(define_insn_reservation "andes_45_vpu_div" 36 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vidiv")) > + "andes_45_vpu_pipe + andes_45_vpu_div * 35") > + > +(define_insn_reservation "andes_45_vpu_madd" 4 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vimuladd,viwmuladd")) > + "andes_45_vpu_pipe + andes_45_vpu_mac") > + > +(define_insn_reservation "andes_45_vpu_merge" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vimerge")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_move" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" > "vimov,vimovvx,vimovxv,vmov,vslideup,vslidedown,vislide1up,vislide1down")) > + "andes_45_vpu_pipe + andes_45_vpu_permut") > + > +(define_insn_reservation "andes_45_vpu_clip" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vnclip")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_falu" 4 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfalu,vfwalu,vfmul,vfwmul")) > + "andes_45_vpu_pipe + andes_45_vpu_mac") > + > +(define_insn_reservation "andes_45_vpu_fdiv" 38 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfdiv,vfsqrt")) > + "andes_45_vpu_pipe + andes_45_vpu_fdiv") > + > +(define_insn_reservation "andes_45_vpu_fmadd" 5 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfmuladd,vfwmuladd")) > + "andes_45_vpu_pipe + andes_45_vpu_mac") > + > +(define_insn_reservation "andes_45_vpu_fminmax" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfminmax")) > + "andes_45_vpu_pipe + andes_45_vpu_fmis") > + > +(define_insn_reservation "andes_45_vpu_fcmp" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfcmp,vfrecp")) > + "andes_45_vpu_pipe + andes_45_vpu_fmis") > + > +(define_insn_reservation "andes_45_vpu_fsgnj" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfsgnj")) > + "andes_45_vpu_pipe + andes_45_vpu_fmis") > + > +(define_insn_reservation "andes_45_vpu_fclass" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfclass")) > + "andes_45_vpu_pipe + andes_45_vpu_fmis") > + > +(define_insn_reservation "andes_45_vpu_fmerge" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfmerge")) > + "andes_45_vpu_pipe + andes_45_vpu_fmis") > + > +(define_insn_reservation "andes_45_vpu_fmove" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfmov,vfmovvf,vfmovfv,vfslide1up,vfslide1down")) > + "andes_45_vpu_pipe + andes_45_vpu_permut") > + > +(define_insn_reservation "andes_45_vpu_fcvt" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" > "vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof, > + > vfncvtitof,vfncvtftoi,vfncvtftof,vfwcvtbf16,vfncvtbf16")) > + "andes_45_vpu_pipe + andes_45_vpu_fmis") > + > +(define_insn_reservation "andes_45_vpu_red" 9 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vired,viwred")) > + "andes_45_vpu_pipe + andes_45_vpu_alu") > + > +(define_insn_reservation "andes_45_vpu_fredu" 6 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfredu,vfwredu")) > + "andes_45_vpu_pipe + andes_45_vpu_mac") > + > +(define_insn_reservation "andes_45_vpu_fredo" 34 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vfredo,vfwredo")) > + "andes_45_vpu_pipe + andes_45_vpu_mac") > + > +(define_insn_reservation "andes_45_vpu_malu" 3 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vmalu")) > + "andes_45_vpu_pipe + andes_45_vpu_mask") > + > +(define_insn_reservation "andes_45_vpu_mask" 4 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vmpop,vmffs,vmsfs,vmiota,vmidx")) > + "andes_45_vpu_pipe + andes_45_vpu_mask") > + > +(define_insn_reservation "andes_45_vpu_gather" 2 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vgather")) > + "andes_45_vpu_pipe + andes_45_vpu_permut") > + > +(define_insn_reservation "andes_45_vpu_compress" 4 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vcompress")) > + "andes_45_vpu_pipe + andes_45_vpu_permut") > + > +(define_insn_reservation "andes_45_vcpu_csr" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "wrvxrm,wrfrm,rdvlenb,rdvl,vsetvl,vsetvl_pre")) > + "andes_45_vpu_pipe") > + > +(define_bypass 1 > + "andes_45_fpu_alu_s, andes_45_fpu_mul_s, andes_45_fpu_mac_s" > + "andes_45_load_wd, andes_45_load_bh, andes_45_store, > + andes_45_fpu_load, andes_45_fpu_store") > + > +(define_bypass 2 > + "andes_45_fpu_alu_d, andes_45_fpu_mul_d, andes_45_fpu_mac_d" > + "andes_45_load_wd, andes_45_load_bh, andes_45_store, > + andes_45_fpu_load, andes_45_fpu_store") > + > +(define_bypass 1 > + "andes_45_fpu_cmp, andes_45_fpu_cvt" > + "andes_45_load_wd, andes_45_load_bh, andes_45_store, > + andes_45_fpu_load, andes_45_fpu_store, andes_45_alu_insn_s, > + andes_45_alu_insn_l, andes_45_xfer") > + > +(define_insn_reservation "andes_45_unknown" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" > "ghost,cpop,clz,ctz,zicond,mvpair,sfb_alu,minu,maxu, > + min,max,clmul,rotate,crypto,condmove,rdfrm")) > + "andes_45_dummies") > + > +(define_insn_reservation "andes_45_vector_unknown" 1 > + (and (eq_attr "tune" "andes_45_series") > + (eq_attr "type" "vclz,vror,vsha2ch,vsm4k,vaesef,vghsh,vsm4r,vsm3c, > + > vaeskf1,vandn,vaesdm,vclmul,vclmulh,vrol,vcpop,vbrev8, > + vsm3me,vbrev,vctz,vgmul,vsha2ms,vaesz,vrev8, > + vaeskf2,vsha2cl,vwsll,vaesdf,vaesem,vfwmaccbf16, > + sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip,vlsegde")) > + "andes_45_vector_dummies") > diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > index e5f093e5819..12b27c95958 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -56,6 +56,7 @@ RISCV_TUNE("size", generic, optimize_size_tune_info) > RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info) > RISCV_TUNE("andes-25-series", andes_25_series, andes_25_tune_info) > RISCV_TUNE("andes-23-series", andes_23_series, andes_23_tune_info) > +RISCV_TUNE("andes-45-series", andes_45_series, andes_45_tune_info) > > #undef RISCV_TUNE > > @@ -188,6 +189,11 @@ RISCV_CORE("andes-n225", > "rv32im_zicsr_zifencei_zca_zcb_zcmp_zcmt_" > RISCV_CORE("andes-d23", > "rv32im_zicsr_zifencei_zicbop_zicbom_zicboz_" > > "zca_zcb_zcmp_zcmt_zba_zbb_zbc_zbs_xandesperf", > "andes-23-series") > +RISCV_CORE("andes-n45", "rv32imc_zicsr_zifencei_xandesperf", > "andes-45-series") > +RISCV_CORE("andes-nx45", "rv64imc_zicsr_zifencei_xandesperf", > "andes-45-series") > +RISCV_CORE("andes-a45", "rv32imafdc_zicsr_zifencei_xandesperf", > "andes-45-series") > +RISCV_CORE("andes-ax45", "rv64imafdc_zicsr_zifencei_xandesperf", > "andes-45-series") > + > RISCV_CORE("spacemit-x60", "rv64imafdcv_zba_zbb_zbc_zbs_zicboz_zicond_" > "zbkc_zfh_zvfh_zvkt_zvl256b_sscofpmf", > "spacemit-x60") > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index c112b1da47c..302e2a860c2 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -63,6 +63,7 @@ enum riscv_microarchitecture_type { > tt_ascalon_d8, > andes_23_series, > andes_25_series, > + andes_45_series, > spacemit_x60, > }; > extern enum riscv_microarchitecture_type riscv_microarchitecture; > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index c3c4021c6a8..63ac9d84183 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -809,6 +809,31 @@ static const struct riscv_tune_param > andes_23_tune_info = { > true, /* > prefer-agnostic. */ > }; > > +/* Costs to use when optimizing for Andes 45 series. */ > +static const struct riscv_tune_param andes_45_tune_info = { > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ > + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ > + {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* int_mul */ > + {COSTS_N_INSNS (24), COSTS_N_INSNS (24)}, /* int_div */ > + 2, /* issue_rate */ > + 3, /* branch_cost */ > + 3, /* memory_cost */ > + 8, /* fmv_cost */ > + false, /* slow_unaligned_access */ > + false, /* vector_unaligned_access > */ > + true, /* > use_divmod_expansion */ > + false, /* overlap_op_by_pieces */ > + false, /* use_zero_stride_load */ > + false, /* > speculative_sched_vsetvl */ > + RISCV_FUSE_NOTHING, /* fusible_ops */ > + NULL, /* vector cost */ > + NULL, /* function_align > */ > + NULL, /* jump_align */ > + NULL, /* loop_align */ > + true, /* > prefer-agnostic. */ > +}; > + > static bool riscv_avoid_shrink_wrapping_separate (); > static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool > *); > static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index aa4631e15a4..6f8cd26e5c9 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -674,7 +674,7 @@ > ;; Keep this in sync with enum riscv_microarchitecture. > (define_attr "tune" > > "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700, > - tt_ascalon_d8,andes_25_series,andes_23_series,spacemit_x60" > + > tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60" > (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) > > ;; Describe a user's asm statement. > @@ -4991,4 +4991,5 @@ > (include "tt-ascalon-d8.md") > (include "andes-23-series.md") > (include "andes-25-series.md") > +(include "andes-45-series.md") > (include "spacemit-x60.md") > diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi > index 8875ff5bcb9..eaf96933b10 100644 > --- a/gcc/doc/riscv-mcpu.texi > +++ b/gcc/doc/riscv-mcpu.texi > @@ -86,4 +86,12 @@ by particular CPU name. Permissible values for this > option are: > > @samp{andes-d23}, > > +@samp{andes-n45}, > + > +@samp{andes-nx45}, > + > +@samp{andes-a45}, > + > +@samp{andes-ax45}, > + > @samp{spacemit-x60}. > diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi > index 578a641b2ba..3e61d11462a 100644 > --- a/gcc/doc/riscv-mtune.texi > +++ b/gcc/doc/riscv-mtune.texi > @@ -62,4 +62,6 @@ particular CPU name. Permissible values for this option > are: > > @samp{andes-23-series}, > > +@samp{andes-45-series}, > + > and all valid options for @option{-mcpu=}. > -- > 2.34.1 > >
