Could you provide testcase to verified select_vl begin generated for VLS mode?
I can't found testcase, I tried param-autovec-mode.c
and select_vl-2.c (with --param=riscv-autovec-mode=V4QI)
and both cases are generated MIN_EXPR rather than SELECT_VL.
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 835947892e9..bbc1697ab63 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4640,8 +4640,22 @@ expand_select_vl (rtx *ops)
> /* We arbitrary picked QImode as inner scalar mode to get vector mode.
> since vsetvl only demand ratio. We let VSETVL PASS to optimize it. */
> scalar_int_mode mode = QImode;
> - machine_mode rvv_mode = get_vector_mode (mode, nunits).require ();
> - emit_insn (gen_no_side_effects_vsetvl_rtx (rvv_mode, ops[0], ops[1]));
> + machine_mode vector_mode = get_vector_mode (mode, nunits).require ();
> + if (riscv_vla_mode_p (vector_mode))
> + emit_insn (gen_no_side_effects_vsetvl_rtx (vector_mode, ops[0], ops[1]));
> + else
> + {
> + /* Emit
> + avl_adj = min (avl, nunits);
> + vsetvl (dest, avl_adj, ...); */
> + gcc_assert (TARGET_ZBB);
^^^ I think we should not assert TARGET_ZBB here, although I that's
because we try to expand UMIN
> + rtx nunits_reg = gen_reg_rtx (Pmode);
> + emit_move_insn (nunits_reg, GEN_INT (nunits.to_constant ()));
> + rtx avl_adj = gen_reg_rtx (Pmode);
> + emit_move_insn (avl_adj, simplify_gen_binary
> + (UMIN, Pmode, ops[1], nunits_reg));
Maybe expand_simple_binop rather than simplify_gen_binary here to
avoid we require ZBB
> + emit_insn (gen_no_side_effects_vsetvl_rtx (vector_mode, ops[0],
> avl_adj));
> + }
> }
>
> /* Return RVV_VUNDEF if the ELSE value is scratch rtx. */
