Hi Andrew,
Thanks for the feedback.
Here is a reduced testcase derived from a bitfield insertion scenario.
static inline unsigned
rot_insert (unsigned x, unsigned y, unsigned n, unsigned mb, unsigned me)
{
if (n)
x = (x << n) | (x >> (32 - n));
unsigned s = -1;
if (n)
s = (s << n) | (s >> (32 - n));
unsigned mask = 0;
mask += 1U << (31 - mb);
mask += 1U << (31 - mb);
mask -= 1U << (31 - me);
mask -= (mb > me);
if (mask & ~s)
return 12345 * y;
return (x & mask) | (y & ~mask);
}
unsigned foo (unsigned x, unsigned y)
{
return rot_insert (x, y, 1, 31, 31);
}
I’ve tested on Power10 and on my local Apple M3 pro, which i assume has Arm
v8.6-A ISA.
If we allow constants (remove INTEGER_CST check), we regress on both.
Assembly Comparison
————————————
I we include INTEGER_CST check and don’t allow constants, we will have XOR AND
XOR form.. which will produce below asms.
Power10
foo:
.LFB1:
.cfi_startproc
.localentry foo,1
rlwimi 4,3,32-31,31,31
rldicl 3,4,0,32
blr
Aarch64
foo:
LFB1:
bfxil w1, w0, 31, 1
mov w0, w1
ret
And if we remove INTEGER_CST check and allow constants, we will have IOR AND
ANDN form., which produces below asm.
Power10
+2 extra instructions
foo:
.LFB1:
.cfi_startproc
.localentry foo,1
rlwinm 4,4,0,0,30
srwi 3,3,31
or 3,3,4
rldicl 3,3,0,32
blr
Aarch64:
Does not match Bitfield extract and insert semantics.
foo:
LFB1:
and w1, w1, -2
orr w0, w1, w0, lsr 31
ret
For Aarch64, i noticed combine generating below pattern failed to match,
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg:SI 112 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
For which we can write a pattern for bfxil which can emit “bfxil w0, w112, #31,
#1” maybe?
But for RS6000, We hit another issue.
We try to merge 3 instructions,
i1 : (set (reg:SI 126 [ _8 ])
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f])))
i2 : (set (reg:SI 127)
(and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe])))
to,
i3 : (set (reg:SI 124 [ _7 ])
(ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127)))
This could have matched just fine, if and only if i1 was the same it was.
But here source of i1,
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f]))
gets transformed to
(subreg:SI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f])) 0).
Because reason being combine performs shift in wider mode.
And later simplify-rtx tries to simplify further and the rtx we endup having,
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])) 0)))
zero_extract, is not allowed in rs6000 backend,
After we try to revert/replace compound zero_extract to normal basic rtx
operations,
we endup having non-matchable code.
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])) 0))).
Because the shift logic is now wrapped in (subreg:SI (and:DI (lshiftrt:DI
...))),
the backend patterns for rlwimi (which expect clear SImode operations) no
longer match.
>> This is the part I am not getting. Specifically the whole `+` part and
>> which instructions are being combined.
>>
>> Is it that we originally had:
>> A = RRotate(P, N)
>> T = (A & C)
>> T1 = (B & ~C)
>> R = T | T1
>>
>> And then we get:
>> T = lshiftrt (P, N)
>> T1 = B & ~C
>> R = T | T1
>>
>> Which then is not recognized as inserting P into B starting at N for
>> the bitmask ?
>> But can't that show up even without the andn pattern?
>> Which means there might be a missing rs6000 pattern for this case?
>>
>> Thanks,
>> Andrew
We do have a pattern for that,
4359 (define_insn "*rotlsi3_insert_4"
4360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4361 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0")
4362 (match_operand:SI 4 "const_int_operand" "n"))
4363 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4364 (match_operand:SI 2 "const_int_operand"
"n"))))]
4365 "INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4])) == 32"
4366 "rlwimi %0,%1,32-%h2,%h2,31"
4367 [(set_attr "type" "insert")])
If we have a form XOR-AND-XOR, which gets transformed to above pattern just
fine via simplify-rtx.cc.
4052 /* If we have (xor (and (xor A B) C) A) with C a constant we can
instead
4053 do (ior (and A ~C) (and B C)) which is a machine instruction on
some
4054 machines, and also has shorter instruction path length. */
Since simplify-rtx handles the XOR-form correctly, restricting this GIMPLE
patch to variables seemed the safest path to avoid these specific Combine
side-effects.
I have attached the combine dumps for reference. I will also work on adding the
GIMPLE testcases and target-supports entries as you requested.
Thanks,
Kishan
;; Function main (main, funcdef_no=1, decl_uid=4601, cgraph_uid=2,
symbol_order=1) (executed once)
scanning new insn with uid = 18.
rescanning insn with uid = 2.
scanning new insn with uid = 19.
rescanning insn with uid = 3.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
main
Dataflow summary:
def_info->table_size = 33, use_info->table_size = 0
;; fully invalidated by EH 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54 [v22] 55
[v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30] 63 [v31]
66 [cc] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74 [p6] 75 [p7] 76 [p8]
77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83 [p15] 84 [fpmr] 85
[ffr] 86 [ffrt]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; exit block uses 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1]
;; ref usage r0={2d,3u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,2u} r30={1d} r31={1d,2u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,2u} r65={1d,1u} r68={1d}
r69={1d} r70={1d} r71={1d} r105={1d,1u} r106={1d,2u} r107={1d,1u} r108={1d,1u}
r109={1d,1u} r110={1d,1u} r111={1d,1u} r112={1d,1u}
;; total ref usage 55{35d,20u,0e} in 10{10 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d1(0){ }d2(1){ }d3(2){ }d4(3){ }d5(4){ }d6(5){
}d7(6){ }d8(7){ }d9(8){ }d10(29){ }d11(30){ }d12(31){ }d13(32){ }d14(33){
}d15(34){ }d16(35){ }d17(36){ }d18(37){ }d19(38){ }d20(39){ }d21(64){ }d22(65){
}d23(68){ }d24(69){ }d25(70){ }d26(71){ }}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; live in
;; live gen 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; live kill
;; lr out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 0 )->[2]->( 1 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(29){ }u-1(31){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 0 [x0] 105 106 107 108 109 110 111 112
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 0 [x0] 105 106 107 108 109 110
;; live kill
;; lr out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 2 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(0){ }u-1(29){ }u-1(31){ }u-1(64){ }}
;; lr in 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; lr use 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; lr def
;; live in 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 16 to worklist
Finished finding needed instructions:
processing block 2 lr out = 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
Adding insn 15 to worklist
Adding insn 10 to worklist
Adding insn 9 to worklist
Adding insn 8 to worklist
Adding insn 7 to worklist
Adding insn 3 to worklist
Adding insn 19 to worklist
Adding insn 2 to worklist
Adding insn 18 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
insn_cost 4 for 18: r111:SI=x0:SI
REG_DEAD x0:SI
insn_cost 4 for 2: r105:SI=r111:SI
REG_DEAD r111:SI
insn_cost 4 for 19: r112:SI=x1:SI
REG_DEAD x1:SI
insn_cost 4 for 3: r106:SI=r112:SI
REG_DEAD r112:SI
insn_cost 4 for 7: r108:SI=r105:SI<-<0x1
REG_DEAD r105:SI
insn_cost 4 for 8: r109:SI=r108:SI^r106:SI
REG_DEAD r108:SI
insn_cost 4 for 9: r110:SI=r109:SI&0x1
REG_DEAD r109:SI
insn_cost 4 for 10: r107:SI=r110:SI^r106:SI
REG_DEAD r110:SI
REG_DEAD r106:SI
insn_cost 4 for 15: x0:SI=r107:SI
REG_DEAD r107:SI
insn_cost 0 for 16: use x0:SI
Trying 2 -> 7:
2: r105:SI=r111:SI
REG_DEAD r111:SI
7: r108:SI=r105:SI<-<0x1
REG_DEAD r105:SI
Successfully matched this instruction:
(set (reg:SI 108 [ x_4 ])
(rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1])))
allowing combination of insns 2 and 7
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 2.
modifying insn i3 7: r108:SI=r111:SI<-<0x1
REG_DEAD r111:SI
deferring rescan insn with uid = 7.
Trying 3 -> 8:
3: r106:SI=r112:SI
REG_DEAD r112:SI
8: r109:SI=r108:SI^r106:SI
REG_DEAD r108:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 109 [ _5 ])
(xor:SI (reg:SI 108 [ x_4 ])
(reg:SI 112 [ y ])))
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 109 [ _5 ])
(xor:SI (reg:SI 108 [ x_4 ])
(reg:SI 112 [ y ])))
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
])
Trying 7 -> 8:
7: r108:SI=r111:SI<-<0x1
REG_DEAD r111:SI
8: r109:SI=r108:SI^r106:SI
REG_DEAD r108:SI
Successfully matched this instruction:
(set (reg:SI 109 [ _5 ])
(xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg/v:SI 106 [ y ])))
allowing combination of insns 7 and 8
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 7.
modifying insn i3 8: r109:SI=r111:SI<-<0x1^r106:SI
REG_DEAD r111:SI
deferring rescan insn with uid = 8.
Trying 3 -> 8:
3: r106:SI=r112:SI
REG_DEAD r112:SI
8: r109:SI=r111:SI<-<0x1^r106:SI
REG_DEAD r111:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 109 [ _5 ])
(xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg:SI 112 [ y ])))
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 109 [ _5 ])
(xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg:SI 112 [ y ])))
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
])
Trying 8 -> 9:
8: r109:SI=r111:SI<-<0x1^r106:SI
REG_DEAD r111:SI
9: r110:SI=r109:SI&0x1
REG_DEAD r109:SI
Failed to match this instruction:
(set (reg:SI 110 [ _6 ])
(and:SI (xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg/v:SI 106 [ y ]))
(const_int 1 [0x1])))
Trying 3, 8 -> 9:
3: r106:SI=r112:SI
REG_DEAD r112:SI
8: r109:SI=r111:SI<-<0x1^r106:SI
REG_DEAD r111:SI
9: r110:SI=r109:SI&0x1
REG_DEAD r109:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 110 [ _6 ])
(and:SI (xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg:SI 112 [ y ]))
(const_int 1 [0x1])))
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 110 [ _6 ])
(and:SI (xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg:SI 112 [ y ]))
(const_int 1 [0x1])))
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
])
Successfully matched this instruction:
(set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ]))
Failed to match this instruction:
(set (reg:SI 110 [ _6 ])
(and:SI (xor:SI (rotate:SI (reg:SI 111 [ x ])
(const_int 1 [0x1]))
(reg:SI 112 [ y ]))
(const_int 1 [0x1])))
Trying 9 -> 10:
9: r110:SI=r109:SI&0x1
REG_DEAD r109:SI
10: r107:SI=r110:SI^r106:SI
REG_DEAD r110:SI
REG_DEAD r106:SI
Failed to match this instruction:
(set (reg:SI 107 [ _7 ])
(xor:SI (and:SI (reg:SI 109 [ _5 ])
(const_int 1 [0x1]))
(reg/v:SI 106 [ y ])))
Trying 8, 9 -> 10:
8: r109:SI=r111:SI<-<0x1^r106:SI
REG_DEAD r111:SI
9: r110:SI=r109:SI&0x1
REG_DEAD r109:SI
10: r107:SI=r110:SI^r106:SI
REG_DEAD r110:SI
REG_DEAD r106:SI
Successfully matched this instruction:
(set (reg:SI 107 [ _7 ])
(ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (zero_extract:DI (subreg:DI (reg:SI 111 [ x ]) 0)
(const_int 1 [0x1])
(const_int 31 [0x1f])) 0)))
allowing combination of insns 8, 9 and 10
original costs 4 + 4 + 4 = 12
replacement cost 12
deferring deletion of insn with uid = 9.
deferring deletion of insn with uid = 8.
modifying insn i3 10:
r107:SI=r106:SI&0xfffffffffffffffe|zero_extract(r111:SI#0,0x1,0x1f)#0
REG_DEAD r111:SI
REG_DEAD r106:SI
deferring rescan insn with uid = 10.
Trying 3 -> 10:
3: r106:SI=r112:SI
REG_DEAD r112:SI
10: r107:SI=r106:SI&0xfffffffffffffffe|zero_extract(r111:SI#0,0x1,0x1f)#0
REG_DEAD r111:SI
REG_DEAD r106:SI
Failed to match this instruction:
(set (reg:SI 107 [ _7 ])
(ior:SI (and:SI (reg:SI 112 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
Trying 10 -> 15:
10: r107:SI=r106:SI&0xfffffffffffffffe|zero_extract(r111:SI#0,0x1,0x1f)#0
REG_DEAD r111:SI
REG_DEAD r106:SI
15: x0:SI=r107:SI
REG_DEAD r107:SI
Failed to match this instruction:
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
Trying 3, 10 -> 15:
3: r106:SI=r112:SI
REG_DEAD r112:SI
10: r107:SI=r106:SI&0xfffffffffffffffe|zero_extract(r111:SI#0,0x1,0x1f)#0
REG_DEAD r111:SI
REG_DEAD r106:SI
15: x0:SI=r107:SI
REG_DEAD r107:SI
Failed to match this instruction:
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg:SI 112 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
Successfully matched this instruction:
(set (reg:SI 107 [ _7 ])
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f])))
Failed to match this instruction:
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg:SI 112 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(reg:SI 107 [ _7 ])))
Trying 15 -> 16:
15: x0:SI=r107:SI
REG_DEAD r107:SI
16: use x0:SI
Failed to match this instruction:
(parallel [
(use (reg:SI 107 [ _7 ]))
(set (reg/i:SI 0 x0)
(reg:SI 107 [ _7 ]))
])
Failed to match this instruction:
(parallel [
(use (reg:SI 107 [ _7 ]))
(set (reg/i:SI 0 x0)
(reg:SI 107 [ _7 ]))
])
Trying 10, 15 -> 16:
10: r107:SI=r106:SI&0xfffffffffffffffe|zero_extract(r111:SI#0,0x1,0x1f)#0
REG_DEAD r111:SI
REG_DEAD r106:SI
15: x0:SI=r107:SI
REG_DEAD r107:SI
16: use x0:SI
Failed to match this instruction:
(parallel [
(use (ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
])
Failed to match this instruction:
(parallel [
(use (ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 111 [ x ])
(const_int 31 [0x1f]))))
])
starting the processing of deferred insns
rescanning insn with uid = 10.
ending the processing of deferred insns
main
Dataflow summary:
;; fully invalidated by EH 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54 [v22] 55
[v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30] 63 [v31]
66 [cc] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74 [p6] 75 [p7] 76 [p8]
77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83 [p15] 84 [fpmr] 85
[ffr] 86 [ffrt]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; exit block uses 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1]
;; ref usage r0={2d,3u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,2u} r30={1d} r31={1d,2u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,2u} r65={1d,1u} r68={1d}
r69={1d} r70={1d} r71={1d} r106={1d,1u} r107={1d,1u} r111={1d,1u} r112={1d,1u}
;; total ref usage 46{31d,15u,0e} in 6{6 regular + 0 call} insns.
;; basic block 2, loop depth 0, count 1073741824 (estimated locally, freq
1.0000), maybe hot
;; prev block 0, next block 1, flags: (RTL, MODIFIED)
;; pred: ENTRY [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(29){ }u-1(31){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 0 [x0] 105 106 107 108 109 110 111 112
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 0 [x0] 105 106 107 108 109 110 111 112
;; live kill
(note 5 0 18 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 18 5 2 2 (set (reg:SI 111 [ x ])
(reg:SI 0 x0 [ x ])) "../testcase/testcase.c":39:39 -1
(expr_list:REG_DEAD (reg:SI 0 x0 [ x ])
(nil)))
(note 2 18 19 2 NOTE_INSN_DELETED)
(insn 19 2 3 2 (set (reg:SI 112 [ y ])
(reg:SI 1 x1 [ y ])) "../testcase/testcase.c":39:39 -1
(expr_list:REG_DEAD (reg:SI 1 x1 [ y ])
(nil)))
(insn 3 19 4 2 (set (reg/v:SI 106 [ y ])
(reg:SI 112 [ y ])) "../testcase/testcase.c":39:39 104 {*movsi_aarch64}
(expr_list:REG_DEAD (reg:SI 112 [ y ])
(nil)))
(note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
(note 7 4 8 2 NOTE_INSN_DELETED)
(note 8 7 9 2 NOTE_INSN_DELETED)
(note 9 8 10 2 NOTE_INSN_DELETED)
(insn 10 9 15 2 (set (reg:SI 107 [ _7 ])
(ior:SI (and:SI (reg/v:SI 106 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (zero_extract:DI (subreg:DI (reg:SI 111 [ x ]) 0)
(const_int 1 [0x1])
(const_int 31 [0x1f])) 0))) "../testcase/testcase.c":35:20
911 {*aarch64_bfxilsi_extrdi}
(expr_list:REG_DEAD (reg:SI 111 [ x ])
(expr_list:REG_DEAD (reg/v:SI 106 [ y ])
(nil))))
(insn 15 10 16 2 (set (reg/i:SI 0 x0)
(reg:SI 107 [ _7 ])) "../testcase/testcase.c":41:1 104 {*movsi_aarch64}
(expr_list:REG_DEAD (reg:SI 107 [ _7 ])
(nil)))
(insn 16 15 0 2 (use (reg/i:SI 0 x0)) "../testcase/testcase.c":41:1 -1
(nil))
;; succ: EXIT [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; lr out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; Function main (main, funcdef_no=1, decl_uid=4601, cgraph_uid=2,
symbol_order=1) (executed once)
scanning new insn with uid = 19.
rescanning insn with uid = 2.
scanning new insn with uid = 20.
rescanning insn with uid = 3.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
main
Dataflow summary:
def_info->table_size = 33, use_info->table_size = 0
;; fully invalidated by EH 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54 [v22] 55
[v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30] 63 [v31]
66 [cc] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74 [p6] 75 [p7] 76 [p8]
77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83 [p15] 84 [fpmr] 85
[ffr] 86 [ffrt]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; exit block uses 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1]
;; ref usage r0={2d,3u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,2u} r30={1d} r31={1d,2u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,2u} r65={1d,1u} r68={1d}
r69={1d} r70={1d} r71={1d} r105={1d,1u} r106={1d,1u} r107={1d,1u} r108={1d,1u}
r109={1d,1u} r110={1d,1u} r112={1d,1u} r113={1d,1u}
;; total ref usage 54{35d,19u,0e} in 10{10 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d1(0){ }d2(1){ }d3(2){ }d4(3){ }d5(4){ }d6(5){
}d7(6){ }d8(7){ }d9(8){ }d10(29){ }d11(30){ }d12(31){ }d13(32){ }d14(33){
}d15(34){ }d16(35){ }d17(36){ }d18(37){ }d19(38){ }d20(39){ }d21(64){ }d22(65){
}d23(68){ }d24(69){ }d25(70){ }d26(71){ }}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; live in
;; live gen 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; live kill
;; lr out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 0 )->[2]->( 1 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(29){ }u-1(31){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 0 [x0] 105 106 107 108 109 110 112 113
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 0 [x0] 105 106 107 108 109 110
;; live kill
;; lr out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 2 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(0){ }u-1(29){ }u-1(31){ }u-1(64){ }}
;; lr in 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; lr use 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; lr def
;; live in 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 17 to worklist
Finished finding needed instructions:
processing block 2 lr out = 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
Adding insn 16 to worklist
Adding insn 11 to worklist
Adding insn 10 to worklist
Adding insn 8 to worklist
Adding insn 7 to worklist
Adding insn 3 to worklist
Adding insn 20 to worklist
Adding insn 2 to worklist
Adding insn 19 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
insn_cost 4 for 19: r112:SI=x0:SI
REG_DEAD x0:SI
insn_cost 4 for 2: r105:SI=r112:SI
REG_DEAD r112:SI
insn_cost 4 for 20: r113:SI=x1:SI
REG_DEAD x1:SI
insn_cost 4 for 3: r106:SI=r113:SI
REG_DEAD r113:SI
insn_cost 4 for 7: r108:SI=r105:SI<-<0x1
REG_DEAD r105:SI
insn_cost 4 for 8: r109:SI=r108:SI&0x1
REG_DEAD r108:SI
insn_cost 4 for 10: r110:SI=r106:SI&0xfffffffffffffffe
REG_DEAD r106:SI
insn_cost 4 for 11: r107:SI=r109:SI|r110:SI
REG_DEAD r110:SI
REG_DEAD r109:SI
insn_cost 4 for 16: x0:SI=r107:SI
REG_DEAD r107:SI
insn_cost 0 for 17: use x0:SI
Trying 2 -> 7:
2: r105:SI=r112:SI
REG_DEAD r112:SI
7: r108:SI=r105:SI<-<0x1
REG_DEAD r105:SI
Successfully matched this instruction:
(set (reg:SI 108 [ x_4 ])
(rotate:SI (reg:SI 112 [ x ])
(const_int 1 [0x1])))
allowing combination of insns 2 and 7
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 2.
modifying insn i3 7: r108:SI=r112:SI<-<0x1
REG_DEAD r112:SI
deferring rescan insn with uid = 7.
Trying 7 -> 8:
7: r108:SI=r112:SI<-<0x1
REG_DEAD r112:SI
8: r109:SI=r108:SI&0x1
REG_DEAD r108:SI
Successfully matched this instruction:
(set (subreg:DI (reg:SI 109 [ _8 ]) 0)
(zero_extract:DI (subreg:DI (reg:SI 112 [ x ]) 0)
(const_int 1 [0x1])
(const_int 31 [0x1f])))
allowing combination of insns 7 and 8
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 7.
modifying insn i3 8: r109:SI#0=zero_extract(r112:SI#0,0x1,0x1f)
REG_DEAD r112:SI
deferring rescan insn with uid = 8.
Trying 3 -> 10:
3: r106:SI=r113:SI
REG_DEAD r113:SI
10: r110:SI=r106:SI&0xfffffffffffffffe
REG_DEAD r106:SI
Successfully matched this instruction:
(set (reg:SI 110)
(and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe])))
allowing combination of insns 3 and 10
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 3.
modifying insn i3 10: r110:SI=r113:SI&0xfffffffffffffffe
REG_DEAD r113:SI
deferring rescan insn with uid = 10.
Trying 8 -> 11:
8: r109:SI#0=zero_extract(r112:SI#0,0x1,0x1f)
REG_DEAD r112:SI
11: r107:SI=r109:SI|r110:SI
REG_DEAD r110:SI
REG_DEAD r109:SI
Successfully matched this instruction:
(set (reg:SI 107 [ _7 ])
(ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110)))
allowing combination of insns 8 and 11
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 8.
modifying insn i3 11: r107:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r112:SI
REG_DEAD r110:SI
deferring rescan insn with uid = 11.
Trying 10 -> 11:
10: r110:SI=r113:SI&0xfffffffffffffffe
REG_DEAD r113:SI
11: r107:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r112:SI
REG_DEAD r110:SI
Failed to match this instruction:
(set (reg:SI 107 [ _7 ])
(ior:SI (and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))))
Trying 11 -> 16:
11: r107:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r112:SI
REG_DEAD r110:SI
16: x0:SI=r107:SI
REG_DEAD r107:SI
Successfully matched this instruction:
(set (reg/i:SI 0 x0)
(ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110)))
allowing combination of insns 11 and 16
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 11.
modifying insn i3 16: x0:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r110:SI
REG_DEAD r112:SI
deferring rescan insn with uid = 16.
Trying 10 -> 16:
10: r110:SI=r113:SI&0xfffffffffffffffe
REG_DEAD r113:SI
16: x0:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r110:SI
REG_DEAD r112:SI
Failed to match this instruction:
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))))
Trying 16 -> 17:
16: x0:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r110:SI
REG_DEAD r112:SI
17: use x0:SI
Failed to match this instruction:
(parallel [
(use (ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110)))
(set (reg/i:SI 0 x0)
(ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110)))
])
Failed to match this instruction:
(parallel [
(use (ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110)))
(set (reg/i:SI 0 x0)
(ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110)))
])
Trying 10, 16 -> 17:
10: r110:SI=r113:SI&0xfffffffffffffffe
REG_DEAD r113:SI
16: x0:SI=r112:SI 0>>0x1f|r110:SI
REG_DEAD r110:SI
REG_DEAD r112:SI
17: use x0:SI
Failed to match this instruction:
(parallel [
(use (ior:SI (and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))))
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))))
])
Failed to match this instruction:
(parallel [
(use (ior:SI (and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))))
(set (reg/i:SI 0 x0)
(ior:SI (and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))))
])
starting the processing of deferred insns
rescanning insn with uid = 10.
rescanning insn with uid = 16.
ending the processing of deferred insns
main
Dataflow summary:
;; fully invalidated by EH 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54 [v22] 55
[v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30] 63 [v31]
66 [cc] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74 [p6] 75 [p7] 76 [p8]
77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83 [p15] 84 [fpmr] 85
[ffr] 86 [ffrt]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap] 68 [p0] 69 [p1] 70 [p2] 71 [p3]
;; exit block uses 0 [x0] 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1]
;; ref usage r0={2d,3u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,2u} r30={1d} r31={1d,2u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,2u} r65={1d,1u} r68={1d}
r69={1d} r70={1d} r71={1d} r110={1d,1u} r112={1d,1u} r113={1d,1u}
;; total ref usage 44{30d,14u,0e} in 5{5 regular + 0 call} insns.
;; basic block 2, loop depth 0, count 1073741824 (estimated locally, freq
1.0000), maybe hot
;; prev block 0, next block 1, flags: (RTL, MODIFIED)
;; pred: ENTRY [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(29){ }u-1(31){ }u-1(64){ }u-1(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 0 [x0] 105 106 107 108 109 110 112 113
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 0 [x0] 105 106 107 108 109 110 112 113
;; live kill
(note 5 0 19 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 19 5 2 2 (set (reg:SI 112 [ x ])
(reg:SI 0 x0 [ x ])) "../testcase/testcase.c":39:39 -1
(expr_list:REG_DEAD (reg:SI 0 x0 [ x ])
(nil)))
(note 2 19 20 2 NOTE_INSN_DELETED)
(insn 20 2 3 2 (set (reg:SI 113 [ y ])
(reg:SI 1 x1 [ y ])) "../testcase/testcase.c":39:39 -1
(expr_list:REG_DEAD (reg:SI 1 x1 [ y ])
(nil)))
(note 3 20 4 2 NOTE_INSN_DELETED)
(note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
(note 7 4 8 2 NOTE_INSN_DELETED)
(note 8 7 10 2 NOTE_INSN_DELETED)
(insn 10 8 11 2 (set (reg:SI 110)
(and:SI (reg:SI 113 [ y ])
(const_int -2 [0xfffffffffffffffe])))
"../testcase/testcase.c":35:20 551 {andsi3}
(expr_list:REG_DEAD (reg:SI 113 [ y ])
(nil)))
(note 11 10 16 2 NOTE_INSN_DELETED)
(insn 16 11 17 2 (set (reg/i:SI 0 x0)
(ior:SI (lshiftrt:SI (reg:SI 112 [ x ])
(const_int 31 [0x1f]))
(reg:SI 110))) "../testcase/testcase.c":41:1 585 {ior_lshrsi3}
(expr_list:REG_DEAD (reg:SI 110)
(expr_list:REG_DEAD (reg:SI 112 [ x ])
(nil))))
(insn 17 16 0 2 (use (reg/i:SI 0 x0)) "../testcase/testcase.c":41:1 -1
(nil))
;; succ: EXIT [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; lr out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; Function foo (foo, funcdef_no=1, decl_uid=4068, cgraph_uid=2, symbol_order=1)
scanning new insn with uid = 19.
rescanning insn with uid = 2.
scanning new insn with uid = 20.
rescanning insn with uid = 3.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
foo
Dataflow summary:
def_info->table_size = 47, use_info->table_size = 0
;; fully invalidated by EH 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8
[8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37
[5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1]
66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12]
77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98
[ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42
[10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8]
73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 3 [3] 4 [4]
;; ref usage r1={1d,2u} r3={2d,3u} r4={1d,1u} r5={1d} r6={1d} r7={1d}
r8={1d} r9={1d} r10={1d} r31={1d,2u} r33={1d} r34={1d} r35={1d} r36={1d}
r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d}
r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d}
r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,1u} r108={1u}
r109={1d,1u} r110={1d,2u} r122={1d,1u} r123={1d,2u} r124={1d,1u} r125={1d,1u}
r126={1d,1u} r127={1d,1u} r128={1d,1u} r129={1d,1u} r130={1d,1u}
;; total ref usage 72{49d,23u,0e} in 11{11 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(1){ }d2(3){ }d3(4){ }d4(5){ }d5(6){ }d6(7){
}d7(8){ }d8(9){ }d9(10){ }d10(31){ }d11(33){ }d12(34){ }d13(35){ }d14(36){
}d15(37){ }d16(38){ }d17(39){ }d18(40){ }d19(41){ }d20(42){ }d21(43){ }d22(44){
}d23(45){ }d24(66){ }d25(67){ }d26(68){ }d27(69){ }d28(70){ }d29(71){ }d30(72){
}d31(73){ }d32(74){ }d33(75){ }d34(76){ }d35(77){ }d36(96){ }d37(99){
}d38(109){ }d39(110){ }}
;; bb 0 artificial_uses: { }
;; lr in 108 [vrsave]
;; lr use
;; lr def 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31
[31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43
[11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74
[10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; live in
;; live gen 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31
[31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43
[11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74
[10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; live kill
;; lr out 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110
[sfp]
;; live out 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
( 0 )->[2]->( 1 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(1){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110
[sfp]
;; lr use 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 110 [sfp]
;; lr def 3 [3] 122 123 124 125 126 127 128 129 130
;; live in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 3 [3] 122 123 124 125 126 127 128
;; live kill
;; lr out 1 [1] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 3 [3] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
( 2 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(1){ }u-1(3){ }u-1(31){ }u-1(108){ }u-1(109){
}u-1(110){ }}
;; lr in 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr def
;; live in 1 [1] 3 [3] 31 [31] 109 [vscr] 110 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 17 to worklist
Finished finding needed instructions:
processing block 2 lr out = 1 [1] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109
[vscr] 110 [sfp]
Adding insn 16 to worklist
Adding insn 11 to worklist
Adding insn 10 to worklist
Adding insn 9 to worklist
Adding insn 8 to worklist
Adding insn 7 to worklist
Adding insn 3 to worklist
Adding insn 20 to worklist
Adding insn 2 to worklist
Adding insn 19 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
insn_cost 4 for 19: r129:DI=%3:DI
REG_DEAD %3:DI
insn_cost 4 for 2: r122:DI=r129:DI
REG_DEAD r129:DI
insn_cost 4 for 20: r130:DI=%4:DI
REG_DEAD %4:DI
insn_cost 4 for 3: r123:DI=r130:DI
REG_DEAD r130:DI
insn_cost 4 for 7: r125:SI=r122:DI#0<-<0x1
REG_DEAD r122:DI
insn_cost 4 for 8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
insn_cost 4 for 9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
insn_cost 4 for 10: r124:SI=r127:SI^r123:DI#0
REG_DEAD r127:SI
REG_DEAD r123:DI
insn_cost 4 for 11: r128:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
insn_cost 4 for 16: %3:DI=r128:DI
REG_DEAD r128:DI
insn_cost 0 for 17: use %3:DI
Trying 2 -> 7:
2: r122:DI=r129:DI
REG_DEAD r129:DI
7: r125:SI=r122:DI#0<-<0x1
REG_DEAD r122:DI
Successfully matched this instruction:
(set (reg:SI 125 [ x_4 ])
(rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1])))
allowing combination of insns 2 and 7
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 2.
modifying insn i3 7: r125:SI=r129:DI#0<-<0x1
REG_DEAD r129:DI
deferring rescan insn with uid = 7.
Trying 3 -> 8:
3: r123:DI=r130:DI
REG_DEAD r130:DI
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 126 [ _5 ])
(xor:SI (reg:SI 125 [ x_4 ])
(subreg:SI (reg:DI 130 [ y ]) 0)))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 126 [ _5 ])
(xor:SI (reg:SI 125 [ x_4 ])
(subreg:SI (reg:DI 130 [ y ]) 0)))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Trying 7 -> 8:
7: r125:SI=r129:DI#0<-<0x1
REG_DEAD r129:DI
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
Failed to match this instruction:
(set (reg:SI 126 [ _5 ])
(xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg/v:DI 123 [ y ]) 0)))
Trying 7, 3 -> 8:
7: r125:SI=r129:DI#0<-<0x1
REG_DEAD r129:DI
3: r123:DI=r130:DI
REG_DEAD r130:DI
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 126 [ _5 ])
(xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg:DI 130 [ y ]) 0)))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 126 [ _5 ])
(xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg:DI 130 [ y ]) 0)))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Successfully matched this instruction:
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
Failed to match this instruction:
(set (reg:SI 126 [ _5 ])
(xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg:DI 130 [ y ]) 0)))
Trying 8 -> 9:
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
Failed to match this instruction:
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (reg:SI 125 [ x_4 ])
(subreg:SI (reg/v:DI 123 [ y ]) 0))
(const_int 1 [0x1])))
Trying 3, 8 -> 9:
3: r123:DI=r130:DI
REG_DEAD r130:DI
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (reg:SI 125 [ x_4 ])
(subreg:SI (reg:DI 130 [ y ]) 0))
(const_int 1 [0x1])))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (reg:SI 125 [ x_4 ])
(subreg:SI (reg:DI 130 [ y ]) 0))
(const_int 1 [0x1])))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Successfully matched this instruction:
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
Failed to match this instruction:
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (reg:SI 125 [ x_4 ])
(subreg:SI (reg:DI 130 [ y ]) 0))
(const_int 1 [0x1])))
Trying 7, 8 -> 9:
7: r125:SI=r129:DI#0<-<0x1
REG_DEAD r129:DI
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
Failed to match this instruction:
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg/v:DI 123 [ y ]) 0))
(const_int 1 [0x1])))
Successfully matched this instruction:
(set (reg:SI 126 [ _5 ])
(rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1])))
Failed to match this instruction:
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (reg:SI 126 [ _5 ])
(subreg:SI (reg/v:DI 123 [ y ]) 0))
(const_int 1 [0x1])))
Trying 7, 3, 8 -> 9:
7: r125:SI=r129:DI#0<-<0x1
REG_DEAD r129:DI
3: r123:DI=r130:DI
REG_DEAD r130:DI
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
Failed to match this instruction:
(parallel [
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg:DI 130 [ y ]) 0))
(const_int 1 [0x1])))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg:DI 130 [ y ]) 0))
(const_int 1 [0x1])))
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
])
Successfully matched this instruction:
(set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ]))
Failed to match this instruction:
(set (reg:SI 127 [ _6 ])
(and:SI (xor:SI (rotate:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1]))
(subreg:SI (reg:DI 130 [ y ]) 0))
(const_int 1 [0x1])))
Trying 9 -> 10:
9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
10: r124:SI=r127:SI^r123:DI#0
REG_DEAD r127:SI
REG_DEAD r123:DI
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(xor:SI (and:SI (reg:SI 126 [ _5 ])
(const_int 1 [0x1]))
(subreg:SI (reg/v:DI 123 [ y ]) 0)))
Trying 8, 9 -> 10:
8: r126:SI=r125:SI^r123:DI#0
REG_DEAD r125:SI
9: r127:SI=r126:SI&0x1
REG_DEAD r126:SI
10: r124:SI=r127:SI^r123:DI#0
REG_DEAD r127:SI
REG_DEAD r123:DI
Successfully matched this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (reg:SI 125 [ x_4 ])
(const_int 1 [0x1]))
(and:SI (subreg:SI (reg/v:DI 123 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))))
allowing combination of insns 8, 9 and 10
original costs 4 + 4 + 4 = 12
replacement cost 4
deferring deletion of insn with uid = 9.
deferring deletion of insn with uid = 8.
modifying insn i3 10: r124:SI=r125:SI&0x1|r123:DI#0&0xfffffffffffffffe
REG_DEAD r125:SI
REG_DEAD r123:DI
deferring rescan insn with uid = 10.
Trying 7 -> 10:
7: r125:SI=r129:DI#0<-<0x1
REG_DEAD r129:DI
10: r124:SI=r125:SI&0x1|r123:DI#0&0xfffffffffffffffe
REG_DEAD r125:SI
REG_DEAD r123:DI
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg/v:DI 123 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(zero_extract:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 1 [0x1])
(const_int 0 [0]))))
Successfully matched this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg/v:DI 123 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 31 [0x1f]))))
allowing combination of insns 7 and 10
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 7.
modifying insn i3 10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
deferring rescan insn with uid = 10.
Trying 3 -> 10:
3: r123:DI=r130:DI
REG_DEAD r130:DI
10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 130 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (zero_extract:DI (reg:DI 129 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])) 0)))
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 130 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (and:DI (lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])) 0)))
Trying 10 -> 11:
10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
11: r128:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg:DI 128 [ _7 ])
(ior:DI (and:DI (reg/v:DI 123 [ y ])
(const_int 4294967294 [0xfffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
Trying 3, 10 -> 11:
3: r123:DI=r130:DI
REG_DEAD r130:DI
10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
11: r128:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg:DI 128 [ _7 ])
(ior:DI (and:DI (reg:DI 130 [ y ])
(const_int 4294967294 [0xfffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
Successfully matched this instruction:
(set (reg:DI 124 [ _7 ])
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f])))
Failed to match this instruction:
(set (reg:DI 128 [ _7 ])
(ior:DI (and:DI (reg:DI 130 [ y ])
(const_int 4294967294 [0xfffffffe]))
(reg:DI 124 [ _7 ])))
Trying 11 -> 16:
11: r128:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
16: %3:DI=r128:DI
REG_DEAD r128:DI
Successfully matched this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ])))
allowing combination of insns 11 and 16
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 11.
modifying insn i3 16: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
deferring rescan insn with uid = 16.
Trying 10 -> 16:
10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
16: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg/i:DI 3 3)
(ior:DI (and:DI (reg/v:DI 123 [ y ])
(const_int 4294967294 [0xfffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
Trying 3, 10 -> 16:
3: r123:DI=r130:DI
REG_DEAD r130:DI
10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
16: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg/i:DI 3 3)
(ior:DI (and:DI (reg:DI 130 [ y ])
(const_int 4294967294 [0xfffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
Successfully matched this instruction:
(set (reg:DI 124 [ _7 ])
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f])))
Failed to match this instruction:
(set (reg/i:DI 3 3)
(ior:DI (and:DI (reg:DI 130 [ y ])
(const_int 4294967294 [0xfffffffe]))
(reg:DI 124 [ _7 ])))
Trying 16 -> 17:
16: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
17: use %3:DI
Failed to match this instruction:
(parallel [
(use (and:DI (subreg:DI (reg:SI 124 [ _7 ]) 0)
(const_int 4294967295 [0xffffffff])))
(set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ])))
])
Failed to match this instruction:
(parallel [
(use (and:DI (subreg:DI (reg:SI 124 [ _7 ]) 0)
(const_int 4294967295 [0xffffffff])))
(set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ])))
])
Trying 10, 16 -> 17:
10: r124:SI=r123:DI#0&0xfffffffffffffffe|r129:DI#0 0>>0x1f
REG_DEAD r129:DI
REG_DEAD r123:DI
16: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
17: use %3:DI
Failed to match this instruction:
(parallel [
(use (ior:DI (and:DI (reg/v:DI 123 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
(set (reg/i:DI 3 3)
(ior:DI (and:DI (reg/v:DI 123 [ y ])
(const_int 4294967294 [0xfffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
])
Failed to match this instruction:
(parallel [
(use (ior:DI (and:DI (reg/v:DI 123 [ y ])
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
(set (reg/i:DI 3 3)
(ior:DI (and:DI (reg/v:DI 123 [ y ])
(const_int 4294967294 [0xfffffffe]))
(lshiftrt:DI (reg:DI 129 [ x ])
(const_int 31 [0x1f]))))
])
starting the processing of deferred insns
rescanning insn with uid = 10.
rescanning insn with uid = 16.
ending the processing of deferred insns
foo
Dataflow summary:
;; fully invalidated by EH 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8
[8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37
[5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1]
66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12]
77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98
[ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42
[10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8]
73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 3 [3] 4 [4]
;; ref usage r1={1d,2u} r3={2d,3u} r4={1d,1u} r5={1d} r6={1d} r7={1d}
r8={1d} r9={1d} r10={1d} r31={1d,2u} r33={1d} r34={1d} r35={1d} r36={1d}
r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d}
r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d}
r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,1u} r108={1u}
r109={1d,1u} r110={1d,2u} r123={1d,1u} r124={1d,1u} r129={1d,1u} r130={1d,1u}
;; total ref usage 61{44d,17u,0e} in 6{6 regular + 0 call} insns.
;; basic block 2, loop depth 0, count 1073741824 (estimated locally, freq
1.0000), maybe hot
;; prev block 0, next block 1, flags: (RTL, MODIFIED)
;; pred: ENTRY [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(1){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110
[sfp]
;; lr use 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 110 [sfp]
;; lr def 3 [3] 122 123 124 125 126 127 128 129 130
;; live in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 3 [3] 122 123 124 125 126 127 128 129 130
;; live kill
(note 5 0 19 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 19 5 2 2 (set (reg:DI 129 [ x ])
(reg:DI 3 3 [ x ])) "../testcase/testcase.c":26:1 709
{*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 3 3 [ x ])
(nil)))
(note 2 19 20 2 NOTE_INSN_DELETED)
(insn 20 2 3 2 (set (reg:DI 130 [ y ])
(reg:DI 4 4 [ y ])) "../testcase/testcase.c":26:1 709
{*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 4 4 [ y ])
(nil)))
(insn 3 20 4 2 (set (reg/v:DI 123 [ y ])
(reg:DI 130 [ y ])) "../testcase/testcase.c":26:1 709
{*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 130 [ y ])
(nil)))
(note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
(note 7 4 8 2 NOTE_INSN_DELETED)
(note 8 7 9 2 NOTE_INSN_DELETED)
(note 9 8 10 2 NOTE_INSN_DELETED)
(insn 10 9 11 2 (set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg/v:DI 123 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (subreg:SI (reg:DI 129 [ x ]) 0)
(const_int 31 [0x1f])))) "../testcase/testcase.c":22:21 255
{*rotlsi3_insert_4}
(expr_list:REG_DEAD (reg:DI 129 [ x ])
(expr_list:REG_DEAD (reg/v:DI 123 [ y ])
(nil))))
(note 11 10 16 2 NOTE_INSN_DELETED)
(insn 16 11 17 2 (set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ]))) "../testcase/testcase.c":28:1 16
{zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 124 [ _7 ])
(nil)))
(insn 17 16 0 2 (use (reg/i:DI 3 3)) "../testcase/testcase.c":28:1 -1
(nil))
;; succ: EXIT [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; lr out 1 [1] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 3 [3] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; Function foo (foo, funcdef_no=1, decl_uid=4067, cgraph_uid=2, symbol_order=1)
scanning new insn with uid = 20.
rescanning insn with uid = 2.
scanning new insn with uid = 21.
rescanning insn with uid = 3.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
foo
Dataflow summary:
def_info->table_size = 47, use_info->table_size = 0
;; fully invalidated by EH 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8
[8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37
[5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1]
66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12]
77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98
[ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42
[10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8]
73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 3 [3] 4 [4]
;; ref usage r1={1d,2u} r3={2d,3u} r4={1d,1u} r5={1d} r6={1d} r7={1d}
r8={1d} r9={1d} r10={1d} r31={1d,2u} r33={1d} r34={1d} r35={1d} r36={1d}
r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d}
r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d}
r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,1u} r108={1u}
r109={1d,1u} r110={1d,2u} r122={1d,1u} r123={1d,1u} r124={1d,1u} r125={1d,1u}
r126={1d,1u} r127={1d,1u} r129={1d,1u} r130={1d,1u} r131={1d,1u}
;; total ref usage 71{49d,22u,0e} in 11{11 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(1){ }d2(3){ }d3(4){ }d4(5){ }d5(6){ }d6(7){
}d7(8){ }d8(9){ }d9(10){ }d10(31){ }d11(33){ }d12(34){ }d13(35){ }d14(36){
}d15(37){ }d16(38){ }d17(39){ }d18(40){ }d19(41){ }d20(42){ }d21(43){ }d22(44){
}d23(45){ }d24(66){ }d25(67){ }d26(68){ }d27(69){ }d28(70){ }d29(71){ }d30(72){
}d31(73){ }d32(74){ }d33(75){ }d34(76){ }d35(77){ }d36(96){ }d37(99){
}d38(109){ }d39(110){ }}
;; bb 0 artificial_uses: { }
;; lr in 108 [vrsave]
;; lr use
;; lr def 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31
[31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43
[11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74
[10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; live in
;; live gen 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31
[31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43
[11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74
[10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; live kill
;; lr out 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110
[sfp]
;; live out 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
( 0 )->[2]->( 1 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(1){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110
[sfp]
;; lr use 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 110 [sfp]
;; lr def 3 [3] 122 123 124 125 126 127 129 130 131
;; live in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 3 [3] 122 123 124 125 126 127 129
;; live kill
;; lr out 1 [1] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 3 [3] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
( 2 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(1){ }u-1(3){ }u-1(31){ }u-1(108){ }u-1(109){
}u-1(110){ }}
;; lr in 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr def
;; live in 1 [1] 3 [3] 31 [31] 109 [vscr] 110 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 18 to worklist
Finished finding needed instructions:
processing block 2 lr out = 1 [1] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109
[vscr] 110 [sfp]
Adding insn 17 to worklist
Adding insn 12 to worklist
Adding insn 11 to worklist
Adding insn 10 to worklist
Adding insn 8 to worklist
Adding insn 7 to worklist
Adding insn 3 to worklist
Adding insn 21 to worklist
Adding insn 2 to worklist
Adding insn 20 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
insn_cost 4 for 20: r130:DI=%3:DI
REG_DEAD %3:DI
insn_cost 4 for 2: r122:DI=r130:DI
REG_DEAD r130:DI
insn_cost 4 for 21: r131:DI=%4:DI
REG_DEAD %4:DI
insn_cost 4 for 3: r123:DI=r131:DI
REG_DEAD r131:DI
insn_cost 4 for 7: r125:SI=r122:DI#0<-<0x1
REG_DEAD r122:DI
insn_cost 4 for 8: r126:SI=r125:SI&0x1
REG_DEAD r125:SI
insn_cost 4 for 10: r127:SI=r123:DI#0&0xfffffffffffffffe
REG_DEAD r123:DI
insn_cost 4 for 11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
insn_cost 4 for 12: r129:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
insn_cost 4 for 17: %3:DI=r129:DI
REG_DEAD r129:DI
insn_cost 0 for 18: use %3:DI
Trying 2 -> 7:
2: r122:DI=r130:DI
REG_DEAD r130:DI
7: r125:SI=r122:DI#0<-<0x1
REG_DEAD r122:DI
Successfully matched this instruction:
(set (reg:SI 125 [ x_4 ])
(rotate:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 1 [0x1])))
allowing combination of insns 2 and 7
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 2.
modifying insn i3 7: r125:SI=r130:DI#0<-<0x1
REG_DEAD r130:DI
deferring rescan insn with uid = 7.
Trying 7 -> 8:
7: r125:SI=r130:DI#0<-<0x1
REG_DEAD r130:DI
8: r126:SI=r125:SI&0x1
REG_DEAD r125:SI
Failed to match this instruction:
(set (reg:SI 126 [ _8 ])
(zero_extract:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 1 [0x1])
(const_int 0 [0])))
Successfully matched this instruction:
(set (reg:SI 126 [ _8 ])
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f])))
allowing combination of insns 7 and 8
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 7.
modifying insn i3 8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
deferring rescan insn with uid = 8.
Trying 3 -> 10:
3: r123:DI=r131:DI
REG_DEAD r131:DI
10: r127:SI=r123:DI#0&0xfffffffffffffffe
REG_DEAD r123:DI
Successfully matched this instruction:
(set (reg:SI 127)
(and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe])))
allowing combination of insns 3 and 10
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 3.
modifying insn i3 10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
deferring rescan insn with uid = 10.
Trying 8 -> 11:
8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (subreg:SI (zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])) 0)
(reg:SI 127)))
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])) 0)
(reg:SI 127)))
Trying 10 -> 11:
10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(reg:SI 126 [ _8 ])))
Trying 10, 8 -> 11:
10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])) 0)))
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])) 0)))
Failed to match this instruction:
(set (reg:DI 127)
(zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])))
Successfully matched this instruction:
(set (reg:DI 127)
(and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])))
Failed to match this instruction:
(set (reg:SI 124 [ _7 ])
(ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(subreg:SI (reg:DI 127) 0)))
Trying 11 -> 12:
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
12: r129:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127))))
Trying 8, 11 -> 12:
8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
12: r129:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (subreg:SI (zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])) 0)
(reg:SI 127))))
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])) 0)
(reg:SI 127))))
Failed to match this instruction:
(set (reg:DI 124 [ _7 ])
(zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])))
Successfully matched this instruction:
(set (reg:DI 124 [ _7 ])
(and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])))
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (subreg:SI (reg:DI 124 [ _7 ]) 0)
(reg:SI 127))))
Trying 10, 11 -> 12:
10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
12: r129:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(reg:SI 126 [ _8 ]))))
Successfully matched this instruction:
(set (reg:SI 124 [ _7 ])
(and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe])))
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (reg:SI 124 [ _7 ])
(reg:SI 126 [ _8 ]))))
Trying 10, 8, 11 -> 12:
10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
12: r129:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f])))))
Successfully matched this instruction:
(set (reg:SI 124 [ _7 ])
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f])))
Failed to match this instruction:
(set (reg:DI 129 [ _7 ])
(zero_extend:DI (ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(reg:SI 124 [ _7 ]))))
Trying 12 -> 17:
12: r129:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
17: %3:DI=r129:DI
REG_DEAD r129:DI
Successfully matched this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ])))
allowing combination of insns 12 and 17
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 12.
modifying insn i3 17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
deferring rescan insn with uid = 17.
Trying 11 -> 17:
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127))))
Trying 8, 11 -> 17:
8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (subreg:SI (zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])) 0)
(reg:SI 127))))
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])) 0)
(reg:SI 127))))
Failed to match this instruction:
(set (reg:DI 124 [ _7 ])
(zero_extract:DI (reg:DI 130 [ x ])
(const_int 32 [0x20])
(const_int 1 [0x1])))
Successfully matched this instruction:
(set (reg:DI 124 [ _7 ])
(and:DI (lshiftrt:DI (reg:DI 130 [ x ])
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])))
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (subreg:SI (reg:DI 124 [ _7 ]) 0)
(reg:SI 127))))
Trying 10, 11 -> 17:
10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(reg:SI 126 [ _8 ]))))
Successfully matched this instruction:
(set (reg:SI 124 [ _7 ])
(and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe])))
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (reg:SI 124 [ _7 ])
(reg:SI 126 [ _8 ]))))
Trying 10, 8, 11 -> 17:
10: r127:SI=r131:DI#0&0xfffffffffffffffe
REG_DEAD r131:DI
8: r126:SI=r130:DI#0 0>>0x1f
REG_DEAD r130:DI
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f])))))
Successfully matched this instruction:
(set (reg:SI 124 [ _7 ])
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f])))
Failed to match this instruction:
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe]))
(reg:SI 124 [ _7 ]))))
Trying 17 -> 18:
17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
18: use %3:DI
Failed to match this instruction:
(parallel [
(use (and:DI (subreg:DI (reg:SI 124 [ _7 ]) 0)
(const_int 4294967295 [0xffffffff])))
(set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ])))
])
Failed to match this instruction:
(parallel [
(use (and:DI (subreg:DI (reg:SI 124 [ _7 ]) 0)
(const_int 4294967295 [0xffffffff])))
(set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ])))
])
Trying 11, 17 -> 18:
11: r124:SI=r126:SI|r127:SI
REG_DEAD r127:SI
REG_DEAD r126:SI
17: %3:DI=zero_extend(r124:SI)
REG_DEAD r124:SI
18: use %3:DI
Failed to match this instruction:
(parallel [
(use (and:DI (subreg:DI (ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127)) 0)
(const_int 4294967295 [0xffffffff])))
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127))))
])
Failed to match this instruction:
(parallel [
(use (and:DI (subreg:DI (ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127)) 0)
(const_int 4294967295 [0xffffffff])))
(set (reg/i:DI 3 3)
(zero_extend:DI (ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127))))
])
starting the processing of deferred insns
rescanning insn with uid = 8.
rescanning insn with uid = 10.
rescanning insn with uid = 17.
ending the processing of deferred insns
foo
Dataflow summary:
;; fully invalidated by EH 0 [0] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8
[8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37
[5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1]
66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12]
77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98
[ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42
[10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8]
73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 3 [3] 4 [4]
;; ref usage r1={1d,2u} r3={2d,3u} r4={1d,1u} r5={1d} r6={1d} r7={1d}
r8={1d} r9={1d} r10={1d} r31={1d,2u} r33={1d} r34={1d} r35={1d} r36={1d}
r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d}
r45={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d}
r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r96={1d} r99={1d,1u} r108={1u}
r109={1d,1u} r110={1d,2u} r124={1d,1u} r126={1d,1u} r127={1d,1u} r130={1d,1u}
r131={1d,1u}
;; total ref usage 63{45d,18u,0e} in 7{7 regular + 0 call} insns.
;; basic block 2, loop depth 0, count 1073741824 (estimated locally, freq
1.0000), maybe hot
;; prev block 0, next block 1, flags: (RTL, MODIFIED)
;; pred: ENTRY [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(1){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110
[sfp]
;; lr use 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 110 [sfp]
;; lr def 3 [3] 122 123 124 125 126 127 129 130 131
;; live in 1 [1] 3 [3] 4 [4] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 3 [3] 122 123 124 125 126 127 129 130 131
;; live kill
(note 5 0 20 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 20 5 2 2 (set (reg:DI 130 [ x ])
(reg:DI 3 3 [ x ])) "../testcase/testcase.c":24:1 709
{*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 3 3 [ x ])
(nil)))
(note 2 20 21 2 NOTE_INSN_DELETED)
(insn 21 2 3 2 (set (reg:DI 131 [ y ])
(reg:DI 4 4 [ y ])) "../testcase/testcase.c":24:1 709
{*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 4 4 [ y ])
(nil)))
(note 3 21 4 2 NOTE_INSN_DELETED)
(note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
(note 7 4 8 2 NOTE_INSN_DELETED)
(insn 8 7 10 2 (set (reg:SI 126 [ _8 ])
(lshiftrt:SI (subreg:SI (reg:DI 130 [ x ]) 0)
(const_int 31 [0x1f]))) "../testcase/testcase.c":20:21 281 {lshrsi3}
(expr_list:REG_DEAD (reg:DI 130 [ x ])
(nil)))
(insn 10 8 11 2 (set (reg:SI 127)
(and:SI (subreg:SI (reg:DI 131 [ y ]) 0)
(const_int -2 [0xfffffffffffffffe])))
"../testcase/testcase.c":20:21 200 {andsi3_mask}
(expr_list:REG_DEAD (reg:DI 131 [ y ])
(nil)))
(insn 11 10 12 2 (set (reg:SI 124 [ _7 ])
(ior:SI (reg:SI 126 [ _8 ])
(reg:SI 127))) "../testcase/testcase.c":20:21 215 {*boolsi3}
(expr_list:REG_DEAD (reg:SI 127)
(expr_list:REG_DEAD (reg:SI 126 [ _8 ])
(nil))))
(note 12 11 17 2 NOTE_INSN_DELETED)
(insn 17 12 18 2 (set (reg/i:DI 3 3)
(zero_extend:DI (reg:SI 124 [ _7 ]))) "../testcase/testcase.c":26:1 16
{zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 124 [ _7 ])
(nil)))
(insn 18 17 0 2 (use (reg/i:DI 3 3)) "../testcase/testcase.c":26:1 -1
(nil))
;; succ: EXIT [always] count:1073741824 (estimated locally, freq
1.0000) (FALLTHRU)
;; lr out 1 [1] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 3 [3] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
