Re:[pushed] [PATCH] LoongArch: Fix ISA base not being updated in loongarch_option_restore [PR123171]

[Lulu Cheng]

在 2025/12/18 下午1:42, WANG Xuerui 写道:

From: WANG Xuerui <g...@xen0n.name>

Fixes switching between LA32S and LA32R base arches with target pragmas
or attributes.

Bootstrapped and regtested on loongarch64-linux-gnu.

        PR target/123171
gcc/ChangeLog:

        * config/loongarch/loongarch.cc (loongarch_option_restore): Add
          missing update to la_target.isa.base.

Hi,

This line should start with a tab, as follows:

```

            * config/loongarch/loongarch.cc (loongarch_option_restore): Add
            missing update to la_target.isa.base.
```

I have made the changes and pushed it to r16-6237.

Thanks.

gcc/testsuite/ChangeLog:

        * gcc.target/loongarch/pr123171.c: New test.

Suggested-by: Lulu Cheng <chengl...@loongson.cn>
Signed-off-by: WANG Xuerui <g...@xen0n.name>
---
  gcc/config/loongarch/loongarch.cc             |  1 +
  gcc/testsuite/gcc.target/loongarch/pr123171.c | 54 +++++++++++++++++++
  2 files changed, 55 insertions(+)
  create mode 100644 gcc/testsuite/gcc.target/loongarch/pr123171.c

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index cc0523f2ab7..6a33d497f31 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -8440,6 +8440,7 @@ loongarch_option_restore (struct gcc_options *,
    la_target.cpu_arch = ptr->x_la_opt_cpu_arch;
    la_target.cpu_tune = ptr->x_la_opt_cpu_tune;

+ la_target.isa.base = loongarch_cpu_default_isa[la_target.cpu_arch].base;

    la_target.isa.fpu = ptr->x_la_opt_fpu;
    la_target.isa.simd = ptr->x_la_opt_simd;
    la_target.isa.evolution = ptr->x_la_isa_evolution;
diff --git a/gcc/testsuite/gcc.target/loongarch/pr123171.c 
b/gcc/testsuite/gcc.target/loongarch/pr123171.c
new file mode 100644
index 00000000000..8c555c2fa26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr123171.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=la32v1.0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** orn_la32r:
+**     nor     \$r5,\$r0,\$r5
+**     or      \$r4,\$r5,\$r4
+**     jr      \$r1
+*/
+#pragma GCC push_options
+#pragma GCC target "arch=la32rv1.0"
+int
+orn_la32r (int a, int b)
+{
+  return a | ~b;
+}
+
+/*
+** orn_la32s_attr:
+**     orn     \$r4,\$r4,\$r5
+**     jr      \$r1
+*/
+int
+__attribute__ ((target ("arch=la32v1.0")))
+orn_la32s_attr (int a, int b)
+{
+  return a | ~b;
+}
+#pragma GCC pop_options
+
+/*
+** orn_la32s:
+**     orn     \$r4,\$r4,\$r5
+**     jr      \$r1
+*/
+int
+orn_la32s (int a, int b)
+{
+  return a | ~b;
+}
+
+/*
+** orn_la32r_attr:
+**     nor     \$r5,\$r0,\$r5
+**     or      \$r4,\$r5,\$r4
+**     jr      \$r1
+*/
+int
+__attribute__ ((target ("arch=la32rv1.0")))
+orn_la32r_attr (int a, int b)
+{
+  return a | ~b;
+}