From: Pan Li <[email protected]>
The vwaddu/vwsubu wx combine patterns take the any_extend by
mistake, it is unsigned so we must leverage zero_extend here.
This PATCH would like to fix this which result in sign_extend
code pattern combine to vwaddu/vwsub.wx.
PR target/123317
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Take zero_extend for
both the vwaddu and vwsubu wx pattern.
Signed-off-by: Pan Li <[email protected]>
---
gcc/config/riscv/autovec-opt.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 95dd10f4834..35476c8c446 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1915,7 +1915,7 @@ (define_insn_and_split "*widen_waddu_wx_<mode>"
[(set (match_operand:VWEXTI_D 0 "register_operand")
(plus:VWEXTI_D
(vec_duplicate:VWEXTI_D
- (any_extend:<VEL>
+ (zero_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand")))
(match_operand:VWEXTI_D 1 "register_operand")))]
"TARGET_VECTOR && TARGET_64BIT && can_create_pseudo_p ()"
@@ -1936,7 +1936,7 @@ (define_insn_and_split "*widen_wsubu_wx_<mode>"
(minus:VWEXTI_D
(match_operand:VWEXTI_D 1 "register_operand")
(vec_duplicate:VWEXTI_D
- (any_extend:<VEL>
+ (zero_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand")))))]
"TARGET_VECTOR && TARGET_64BIT && can_create_pseudo_p ()"
"#"
--
2.43.0
