On Tue, Jan 6, 2026 at 5:51 PM Eric Botcazou <[email protected]> wrote: > > > OK, though I wonder if there's not more issues elsewhere. I wasn't aware > > of SPARC supporting masking of vector operations. I also wonder how > > aarch64_be handles this with its VnBImode vectors (that is, how the HW > > lays out lanes there). > > It hadn't until GCC 14, but someone forced it to under PR target/114189. ;-)
Heh ;) I probably asked before - but I can only find syntactic documentation of VIS, not semantics (I find a few compare instructions involving GPRs, possibly for the result). Is there a public ISA spec that has all the details somewhere? Richard. > -- > Eric Botcazou > >
