On 1/7/2026 3:51 AM, Luis Silva wrote:
This patch series adds support for the Synopsys RHX-100 series to the RISC-V GCC
backend. The RHX-100 is a dual-issue, 10-stage, in-order processor with
instruction fusion capabilities.
The series introduces:
1. A pipeline description for the RHX-100 series.
2. Fusion patterns added to riscv_macro_fusion_pair_p.
3. The TARGET_SCHED_FUSION_PRIORITY hook for improved load/store fusion.
4. Scheduler hooks and state tracking for dual-issue and fusion-aware
scheduling.
5. Instruction patterns for 32-bit multiply-add and bit-extract fusion.
The series was regtested with the generic mtune as a whole, not independently.
Luis Silva (5):
RISC-V: Add Synopsys RHX-100 series pipeline description.
RISC-V: Implement riscv_macro_fusion_pair_p for Synopsys RHX-100
series.
RISC-V: Implement TARGET_SCHED_FUSION_PRIORITY for Synopsys RHX-100
series.
RISC-V: Implement scheduling for Synopsys RHX-100 series.
RISC-V: Add instruction patterns for 32-bit multiply-add and
bit-extract fusion.
This will need to defer to gcc-17.
jeff
