[PATCH] RISC-V: Support Zalasr extension.

[Jiawei]

This patch support RISC-V Zalasr[1](load-acquire/store-release) extension. 
Based on Edwin Lu's old patch:
https://patchwork.sourceware.org/project/gcc/patch/20250410214940.2712673-1-e...@rivosinc.com/

[1] 
https://docs.riscv.org/reference/isa/extensions/zalasr/_attachments/riscv-zalasr.pdf

Co-Authored-by: Edwin Lu <e...@rivosinc.com>

gcc/ChangeLog:

        * config/riscv/riscv-ext.def: New extension.
        * config/riscv/riscv-ext.opt: Ditto.
        * config/riscv/sync-rvwmo.md: Add check for zalasr.
        * config/riscv/sync-ztso.md: Ditto.
        * doc/riscv-ext.texi: New extension.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/amo/a-rvwmo-fence.c: Disable zalasr from -march.
        * gcc.target/riscv/amo/a-rvwmo-load-acquire.c: Ditto.
        * gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: Ditto.
        * gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: Ditto.
        * gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Ditto.
        * gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Ditto.
        * gcc.target/riscv/amo/a-rvwmo-store-release.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-fence.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-load-acquire.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-load-relaxed.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-load-seq-cst.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-store-relaxed.c: Ditto.
        * gcc.target/riscv/amo/a-ztso-store-release.c: Ditto.
        * gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c: Ditto.
        * gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c: Ditto.
        * gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: Ditto.
        * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Ditto.
        * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: Ditto.
        * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: Ditto.
        * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: Ditto.
        * gcc.target/riscv/amo/zabha-zacas-atomic-cas.c: Ditto.
        * gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: Ditto.
        * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: Ditto.
        * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: Ditto.
        * gcc.target/riscv/amo/zacas-char-requires-zabha.c: Ditto.
        * gcc.target/riscv/amo/zacas-char-requires-zacas.c: Ditto.
        * gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c: 
Ditto.
        * 
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c:
 Ditto.
        * 
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: Ditto.
        * 
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c:
 Ditto.
        * 
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: 
Ditto.
        * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: Ditto.
        * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: Ditto.
        * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: 
Ditto.
        * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c: Ditto.
        * 
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: 
Ditto.
        * 
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c: Ditto.
        * 
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: 
Ditto.
        * 
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: 
Ditto.
        * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: 
Ditto.
        * lib/target-supports.exp: Add zalasr checks.
        * gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c: New test.
        * gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c: New test.
        * gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c: New test.
        * gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c: New test.
        * gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c: New test.
        * gcc.target/riscv/amo/zalasr-rvwmo-store-release.c: New test.
        * gcc.target/riscv/amo/zalasr-ztso-load-acquire.c: New test.
        * gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c: New test.
        * gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c: New test.
        * gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c: New test.
        * gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: New test.
        * gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.

---
 gcc/config/riscv/riscv-ext.def                | 13 ++++
 gcc/config/riscv/riscv-ext.opt                |  2 +
 gcc/config/riscv/sync-rvwmo.md                | 13 ++--
 gcc/config/riscv/sync-ztso.md                 | 13 ++--
 gcc/doc/riscv-ext.texi                        |  4 ++
 .../gcc.target/riscv/amo/a-rvwmo-fence.c      |  1 +
 .../riscv/amo/a-rvwmo-load-acquire.c          |  1 +
 .../riscv/amo/a-rvwmo-load-relaxed.c          |  1 +
 .../riscv/amo/a-rvwmo-load-seq-cst.c          |  1 +
 .../riscv/amo/a-rvwmo-store-compat-seq-cst.c  |  1 +
 .../riscv/amo/a-rvwmo-store-relaxed.c         |  1 +
 .../riscv/amo/a-rvwmo-store-release.c         |  1 +
 .../gcc.target/riscv/amo/a-ztso-fence.c       |  1 +
 .../riscv/amo/a-ztso-load-acquire.c           |  1 +
 .../riscv/amo/a-ztso-load-relaxed.c           |  1 +
 .../riscv/amo/a-ztso-load-seq-cst.c           |  1 +
 .../riscv/amo/a-ztso-store-compat-seq-cst.c   |  1 +
 .../riscv/amo/a-ztso-store-relaxed.c          |  1 +
 .../riscv/amo/a-ztso-store-release.c          |  1 +
 .../riscv/amo/zaamo-preferred-over-zalrsc.c   |  1 +
 .../riscv/amo/zaamo-rvwmo-amo-add-int.c       |  1 +
 .../riscv/amo/zaamo-ztso-amo-add-int.c        |  1 +
 .../riscv/amo/zabha-rvwmo-all-amo-ops-char.c  |  1 +
 .../riscv/amo/zabha-rvwmo-all-amo-ops-short.c |  1 +
 .../riscv/amo/zabha-rvwmo-amo-add-char.c      |  1 +
 .../riscv/amo/zabha-rvwmo-amo-add-short.c     |  1 +
 .../riscv/amo/zabha-zacas-atomic-cas.c        |  1 +
 .../amo/zabha-zacas-preferred-over-zalrsc.c   |  1 +
 .../riscv/amo/zabha-ztso-amo-add-char.c       |  1 +
 .../riscv/amo/zabha-ztso-amo-add-short.c      |  1 +
 .../riscv/amo/zacas-char-requires-zabha.c     |  1 +
 .../riscv/amo/zacas-char-requires-zacas.c     |  1 +
 .../riscv/amo/zacas-preferred-over-zalrsc.c   |  1 +
 ...acas-rvwmo-compare-exchange-char-acq-rel.c |  1 +
 ...acas-rvwmo-compare-exchange-char-acquire.c |  1 +
 ...acas-rvwmo-compare-exchange-char-relaxed.c |  1 +
 ...acas-rvwmo-compare-exchange-char-release.c |  1 +
 ...acas-rvwmo-compare-exchange-char-seq-cst.c |  1 +
 ...-exchange-compatability-mapping-no-fence.c |  1 +
 ...-compare-exchange-compatability-mapping.cc |  1 +
 ...zacas-rvwmo-compare-exchange-int-acq-rel.c |  1 +
 ...zacas-rvwmo-compare-exchange-int-acquire.c |  1 +
 ...zacas-rvwmo-compare-exchange-int-relaxed.c |  1 +
 ...zacas-rvwmo-compare-exchange-int-release.c |  1 +
 ...zacas-rvwmo-compare-exchange-int-seq-cst.c |  1 +
 ...cas-rvwmo-compare-exchange-short-acq-rel.c |  1 +
 ...cas-rvwmo-compare-exchange-short-acquire.c |  1 +
 ...cas-rvwmo-compare-exchange-short-relaxed.c |  1 +
 ...cas-rvwmo-compare-exchange-short-release.c |  1 +
 ...cas-rvwmo-compare-exchange-short-seq-cst.c |  1 +
 .../amo/zacas-ztso-compare-exchange-char.c    |  1 +
 ...-exchange-compatability-mapping-no-fence.c |  1 +
 ...-compare-exchange-compatability-mapping.cc |  1 +
 .../zacas-ztso-compare-exchange-int-seq-cst.c |  1 +
 .../amo/zacas-ztso-compare-exchange-int.c     |  1 +
 ...acas-ztso-compare-exchange-short-seq-cst.c |  1 +
 .../amo/zacas-ztso-compare-exchange-short.c   |  1 +
 .../riscv/amo/zalasr-rvwmo-load-acquire.c     | 62 ++++++++++++++++
 .../riscv/amo/zalasr-rvwmo-load-relaxed.c     | 62 ++++++++++++++++
 .../riscv/amo/zalasr-rvwmo-load-seq-cst.c     | 72 +++++++++++++++++++
 .../amo/zalasr-rvwmo-store-compat-seq-cst.c   | 63 ++++++++++++++++
 .../riscv/amo/zalasr-rvwmo-store-relaxed.c    | 62 ++++++++++++++++
 .../riscv/amo/zalasr-rvwmo-store-release.c    | 62 ++++++++++++++++
 .../riscv/amo/zalasr-ztso-load-acquire.c      | 62 ++++++++++++++++
 .../riscv/amo/zalasr-ztso-load-relaxed.c      | 62 ++++++++++++++++
 .../riscv/amo/zalasr-ztso-load-seq-cst.c      | 67 +++++++++++++++++
 .../amo/zalasr-ztso-store-compat-seq-cst.c    | 63 ++++++++++++++++
 .../riscv/amo/zalasr-ztso-store-relaxed.c     | 62 ++++++++++++++++
 .../riscv/amo/zalasr-ztso-store-release.c     | 62 ++++++++++++++++
 .../riscv/amo/zalrsc-rvwmo-amo-add-int.c      |  1 +
 ...wmo-compare-exchange-int-acquire-release.c |  1 +
 ...alrsc-rvwmo-compare-exchange-int-acquire.c |  1 +
 ...alrsc-rvwmo-compare-exchange-int-consume.c |  1 +
 ...alrsc-rvwmo-compare-exchange-int-relaxed.c |  1 +
 ...alrsc-rvwmo-compare-exchange-int-release.c |  1 +
 ...wmo-compare-exchange-int-seq-cst-relaxed.c |  1 +
 ...alrsc-rvwmo-compare-exchange-int-seq-cst.c |  1 +
 ...alrsc-rvwmo-subword-amo-add-char-acq-rel.c |  1 +
 ...alrsc-rvwmo-subword-amo-add-char-acquire.c |  1 +
 ...alrsc-rvwmo-subword-amo-add-char-relaxed.c |  1 +
 ...alrsc-rvwmo-subword-amo-add-char-release.c |  1 +
 ...alrsc-rvwmo-subword-amo-add-char-seq-cst.c |  1 +
 .../riscv/amo/zalrsc-ztso-amo-add-int.c       |  1 +
 ...tso-compare-exchange-int-acquire-release.c |  1 +
 ...zalrsc-ztso-compare-exchange-int-acquire.c |  1 +
 ...zalrsc-ztso-compare-exchange-int-consume.c |  1 +
 ...zalrsc-ztso-compare-exchange-int-relaxed.c |  1 +
 ...zalrsc-ztso-compare-exchange-int-release.c |  1 +
 ...tso-compare-exchange-int-seq-cst-relaxed.c |  1 +
 ...zalrsc-ztso-compare-exchange-int-seq-cst.c |  1 +
 ...zalrsc-ztso-subword-amo-add-char-acq-rel.c |  1 +
 ...zalrsc-ztso-subword-amo-add-char-acquire.c |  1 +
 ...zalrsc-ztso-subword-amo-add-char-relaxed.c |  1 +
 ...zalrsc-ztso-subword-amo-add-char-release.c |  1 +
 ...zalrsc-ztso-subword-amo-add-char-seq-cst.c |  1 +
 gcc/testsuite/lib/target-supports.exp         | 20 +++++-
 96 files changed, 895 insertions(+), 9 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 1621e81b011..1993e899148 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -545,6 +545,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ 26,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ zalasr,
+  /* UPPERCASE_NAME */ ZALASR,
+  /* FULL_NAME */ "Atomic load-acquire and store-release extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ za,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ zalrsc,
   /* UPPERCASE_NAME */ ZALRSC,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 18402ea97c7..7bf3d4effc6 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -176,6 +176,8 @@ Mask(ZABHA) Var(riscv_za_subext)
 
 Mask(ZACAS) Var(riscv_za_subext)
 
+Mask(ZALASR) Var(riscv_za_subext)
+
 Mask(ZALRSC) Var(riscv_za_subext)
 
 Mask(ZAWRS) Var(riscv_za_subext)
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index ed65cecf514..be2a7303854 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -61,11 +61,12 @@
       return "fence\trw,rw\;"
             "<load>\t%0,%1\;"
             "fence\tr,rw";
+    if (TARGET_ZALASR && model == MEMMODEL_ACQUIRE)
+      return "<load>.aq\t%0,%1";
     if (model == MEMMODEL_ACQUIRE)
       return "<load>\t%0,%1\;"
             "fence\tr,rw";
-    else
-      return "<load>\t%0,%1";
+    return "<load>\t%0,%1";
   }
   [(set_attr "type" "multi")
    (set (attr "length")
@@ -86,6 +87,10 @@
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
 
+    if (TARGET_ZALASR
+       && (model == MEMMODEL_RELEASE || model == MEMMODEL_SEQ_CST))
+      return "<store>.rl\t%z1,%0";
+
     if (model == MEMMODEL_SEQ_CST)
       return "fence\trw,w\;"
             "<store>\t%z1,%0\;"
@@ -93,8 +98,8 @@
     if (model == MEMMODEL_RELEASE)
       return "fence\trw,w\;"
             "<store>\t%z1,%0";
-    else
-      return "<store>\t%z1,%0";
+
+    return "<store>\t%z1,%0";
   }
   [(set_attr "type" "multi")
    (set (attr "length")
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 689025a4b21..4f3eddd0da0 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -51,11 +51,13 @@
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
 
+    /* Ignoring RCsc atomic load-acquire on MEMMODEL_SEQ_CST due to
+       Note 3 abi break for when TARGET_ZALASR is enabled.  */
     if (model == MEMMODEL_SEQ_CST)
       return "fence\trw,rw\;"
             "<load>\t%0,%1";
-    else
-      return "<load>\t%0,%1";
+
+    return "<load>\t%0,%1";
   }
   [(set_attr "type" "multi")
    (set (attr "length")
@@ -74,11 +76,14 @@
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
 
+    if (TARGET_ZALASR && (model == MEMMODEL_SEQ_CST))
+      return "<store>.rl\t%z1,%0";
+
     if (model == MEMMODEL_SEQ_CST)
       return "<store>\t%z1,%0\;"
             "fence\trw,rw";
-    else
-      return "<store>\t%z1,%0";
+
+    return "<store>\t%z1,%0";
   }
   [(set_attr "type" "multi")
    (set (attr "length")
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 36b4dff31ff..bf4f56a6201 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -158,6 +158,10 @@
 @tab 1.0
 @tab Atomic compare-and-swap instructions extension
 
+@item @samp{zalasr}
+@tab 1.0
+@tab Atomic load-acquire and store-release extension
+
 @item @samp{zalrsc}
 @tab 1.0
 @tab Load-reserved/store-conditional subset of the A extension
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
index 6803bf92aa3..3947923e6ea 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
@@ -2,6 +2,7 @@
 /* Verify that fence mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
index 93a0c68ae8a..810e7959508 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
index 2403d53c131..01a1e3c5c86 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
index 31b35cf9f6a..ee728675155 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
index 45c9abb1425..b3ec4e1061b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
@@ -3,6 +3,7 @@
    mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
index 4b321b2b75f..2f224f993de 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
index a2a617c4d15..6daca225d24 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
index 153f6ef8a3d..d432cdc2ffc 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
@@ -2,6 +2,7 @@
 /* Verify that fence mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
index 76a12059f39..f221169def9 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
index c4ee56e2cc0..2ee094679eb 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
index 7163311433c..8ad64e6579c 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
index 2f4c9124aaf..a1cefbb1109 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
@@ -3,6 +3,7 @@
    mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
index d469bf348d9..939ad757462 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
index 3a275740401..bb97b8a6d52 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c 
b/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c
index dae30c32e01..09089c8e980 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_zaamo } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c 
b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c
index ca40a49f9b5..9d365fc0778 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zaamo } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c 
b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
index 8ebdc61992e..56122bc1f05 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
index 58211207186..845e07e8866 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
@@ -3,6 +3,7 @@
 /* { dg-options "-Wno-address-of-packed-member" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tamoadd.b" } } */
 /* { dg-final { scan-assembler "\tamoadd.b.aq" } } */
 /* { dg-final { scan-assembler "\tamoadd.b.rl" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
index c846ca48d72..43c79aca19b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
@@ -3,6 +3,7 @@
 /* { dg-options "-Wno-address-of-packed-member" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tamoadd.h" } } */
 /* { dg-final { scan-assembler "\tamoadd.h.aq" } } */
 /* { dg-final { scan-assembler "\tamoadd.h.rl" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c
index a75c102196d..6acde263132 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c
index 7755bb84784..31eaa9feb18 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
index d3d84fd3088..851d81239f7 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 
 _Bool b;
 void atomic_bool_cmpxchg()
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c
index a06e195c6d4..6c19c90a9f3 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c
@@ -5,6 +5,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
index bcd7477c673..f3c1a26166f 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
index c4e8c9cf3ef..b632094acfe 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c
index c7d6e7c578b..82f9942b110 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c
@@ -5,6 +5,7 @@
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_zabha } */
 /* { dg-remove-options riscv_zalrsc } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tcall\t" } } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c
index d0cf14432fe..9c77848c680 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c
@@ -5,6 +5,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_zacas } */
 /* { dg-remove-options riscv_zalrsc } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tcall\t" } } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c
index 9a995cca37f..7a8200eb08b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c
@@ -4,6 +4,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
index b76385b4d26..fea3c53757b 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.aqrl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
index 62ecf7b5fff..ab67c49234d 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.aq\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
index 21c960c893b..10dd0f7399f 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
index 6b4083376ee..b4968c12a4c 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.rl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
index 289bdf44e9f..4416d457c7e 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.aqrl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
index 99fd7577a48..e4f5eeb47dc 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
@@ -7,6 +7,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tfence" } } */
 
 void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int 
qux)
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
index c8d81299197..a5058a273c2 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
@@ -7,6 +7,7 @@
 /* { dg-options "-O3 -std=c++17" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c
index 1b55c934962..fe01950607d 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.aqrl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c
index 8182360f244..15afd4a8a2f 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.aq\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c
index fb2a7b4f55a..3e9c110a0f0 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c
index 756f5cbe7d1..506eb02615a 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.rl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c
index 1c5b4ac0e2f..6c7981b0832 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.aqrl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
index 2987eb3615d..287dd3fddba 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.aqrl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
index 505791090be..165142b7041 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.aq\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
index a85694e26c8..4be9a566d0a 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
index e8e9aae0265..12d5b506721 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.rl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
index d676d378e06..c219ea03b4e 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.aqrl\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
index 183dc4020c7..9ede267eea2 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\t" 8 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
index 2712eff5107..65b6e392fcf 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
@@ -7,6 +7,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tfence" } } */
 
 void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int 
qux)
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
index 560172bfbed..8556837793c 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
@@ -7,6 +7,7 @@
 /* { dg-options "-O3 -std=c++17" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
index 1ee6cc20218..766ae162253 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
index 2c332623a95..6d2a17f9199 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 8 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
index 1938448183c..7ab8ce0e98f 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c 
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
index 69fe5ae3eac..3089e68ab71 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\t" 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
new file mode 100644
index 00000000000..aea6bc6822a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_acquire:
+**     l[wd].aq\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_acquire (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_int_acquire:
+**     lw.aq\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_acquire (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_short_acquire:
+**     lh.aq\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_acquire (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_char_acquire:
+**     lb.aq\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_acquire (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_bool_acquire:
+**     lb.aq\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_acquire (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
new file mode 100644
index 00000000000..eee5f8d5bb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_relaxed (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_relaxed (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_short_relaxed:
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_relaxed (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_char_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_relaxed (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_bool_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
new file mode 100644
index 00000000000..54ad19b1071
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_seq_cst:
+**     fence\trw,rw
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_int_seq_cst:
+**     fence\trw,rw
+**     lw\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_short_seq_cst:
+**     fence\trw,rw
+**     lh\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_char_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_bool_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
new file mode 100644
index 00000000000..7f40d443bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended compatibility
+   mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_seq_cst:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd].rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_int_seq_cst:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_short_seq_cst:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_char_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_bool_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
new file mode 100644
index 00000000000..d0127e53baa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd]\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_relaxed (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_relaxed (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_short_relaxed:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_relaxed (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_char_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_relaxed (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_bool_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
new file mode 100644
index 00000000000..6174718fe2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_release:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd].rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_release (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_int_release:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_release (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_short_release:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_release (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_char_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_release (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_bool_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_release (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
new file mode 100644
index 00000000000..2e71ea38678
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_acquire:
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_acquire (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_int_acquire:
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_acquire (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_short_acquire:
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_acquire (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_char_acquire:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_acquire (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_bool_acquire:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_acquire (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
new file mode 100644
index 00000000000..ce2c41563a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_relaxed (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_relaxed (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_short_relaxed:
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_relaxed (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_char_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_relaxed (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_bool_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
new file mode 100644
index 00000000000..70038f81c13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_seq_cst:
+**     fence\trw,rw
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_int_seq_cst:
+**     fence\trw,rw
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_short_seq_cst:
+**     fence\trw,rw
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_char_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_bool_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
new file mode 100644
index 00000000000..085f94e5d42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended compatibility
+   mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_seq_cst:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd].rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_int_seq_cst:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_short_seq_cst:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_char_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_bool_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
new file mode 100644
index 00000000000..cb68849291b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd]\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_relaxed (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_relaxed (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_short_relaxed:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_relaxed (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_char_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_relaxed (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_bool_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
new file mode 100644
index 00000000000..b5cc2e967d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_release:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd]\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_release (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_int_release:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_release (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_short_release:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_release (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_char_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_release (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_bool_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_release (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c
index 0dfe816ba29..c0e9673925b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_zaamo } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
index 9a5616f8916..621c79ac32c 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* Mixed mappings need to be unioned.  */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
index a24234855e9..b449607553e 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
index 18f53c83a38..63bb275def1 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
index c7a43ecd323..40dcdf6be8c 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
index 302fca2ca17..9161f2acc11 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
index e62002d267a..769ce56d9a2 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
index c047d509aaf..55a13e12680 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
index 33b70acb15c..c453115362e 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
index e173296bcfc..7eae408a6b4 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
index f544d677219..6ded40d5a18 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
index bb34873feeb..919057bdd6d 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
index d8991ee1a84..4aec4f259aa 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
index 658b0404b97..6573b3a6459 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zaamo } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
index 496af8bfd7d..1a9a8e4a36a 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
index 737e3eb3d68..b9a92d39f8a 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
index 51b3b5a8dc7..0ce1d3eefc2 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
index 9a41410a57b..1aba82e5286 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
index ee778a760d1..2bf0cc16b33 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
index 6fbe943b316..532cb18dda7 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
index a361c10086d..559f5a18866 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
index 7c9187e52b5..ff3a5f790a3 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
index 675043f9c61..1828b47c4d8 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
index 7bf9eb0a7f7..3b76458b7b9 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
index 6b78ce74b00..1a81054cc02 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
index 14fadf1e3fe..b6eacb72572 100644
--- 
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
+++ 
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 2b450669c3d..1a42cb7f438 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2105,6 +2105,16 @@ proc check_effective_target_riscv_zacas { } {
     }]
 }
 
+# Return 1 if the target arch supports the atomic-acquire and load-release 
extension, 0 otherwise.
+# Cache the result.
+proc check_effective_target_riscv_zalasr { } {
+    return [check_no_compiler_messages riscv_ext_zalasr assembly {
+       #ifndef __riscv_zalasr
+       #error "Not __riscv_zalasr"
+       #endif
+    }]
+}
+
 # Return 1 if the target arch supports the double precision floating point
 # extension, 0 otherwise.  Cache the result.
 
@@ -2511,7 +2521,7 @@ proc check_effective_target_riscv_v_misalign_ok { } {
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbkb zbkc 
zbs zvbb zvfh ztso zaamo zalrsc zabha zacas } {
+    foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbkb zbkc 
zbs zvbb zvfh ztso zaamo zalrsc zalasr zabha zacas } {
        if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map 
[list DEF __riscv_$ext] {
                #ifndef DEF
                #error "Not DEF"
@@ -2708,6 +2718,14 @@ proc remove_options_for_riscv_zalrsc { flags } {
     return $modified_flags
 }
 
+proc add_options_for_riscv_zalasr { flags } {
+    return [add_options_for_riscv_z_ext zalasr $flags]
+}
+
+proc remove_options_for_riscv_zalasr { flags } {
+    return [remove_options_for_riscv_z_ext zalasr $flags]
+}
+
 proc add_options_for_riscv_zabha { flags } {
     return [add_options_for_riscv_z_ext zabha $flags]
 }
-- 
2.43.0