This is a preparatory patch for the bulk of the SVE2.2/SME2.2 support
series, putting into place some machinery used by the later patches. This
includes TARGET_* constants that are set based on ISA flags,
__ARM_FEATURE_* macros, and new match_test definitions that are used to
enable/disable individual instruction patterns/alternatives.
On the testsuite side of things, this patch adds some rudimentary tests
that check that __ARM_FEATURE_* macros are correctly defined for various
combinations of target flags, as well as two new effective-target checks
in lib/target-supports.exp, one for each of SVE2.2-capable HW and
toolchain.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Emit definitions for __ARM_FEATURE_{SVE,SME}2p2.
* config/aarch64/aarch64.h (TARGET_SVE2p2): New macro.
(TARGET_SME2p2): Likewise.
* config/aarch64/aarch64.md (arches): Add sve2p2_or_sme2p2 enum
constant.
(arch): Add test for sve2p2_or_sme2p2.
* doc/invoke.texi: Document sve2p2 and sme2p2 extensions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pragma_cpp_predefs_3.c: Add SVE2p2 tests.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add SME2p2 test.
* lib/target-supports.exp
(check_effective_target_aarch64_sve2p2_hw): New target check.
(check_effective_target_aarch64_sve2p2_ok): New target check.
(exts_sve2): Add sme2p2.
---
gcc/config/aarch64/aarch64-c.cc | 2 +
gcc/config/aarch64/aarch64.h | 6 ++
gcc/config/aarch64/aarch64.md | 7 +-
gcc/doc/invoke.texi | 5 +
.../gcc.target/aarch64/pragma_cpp_predefs_3.c | 100 ++++++++++++++++++
.../gcc.target/aarch64/pragma_cpp_predefs_4.c | 14 +++
gcc/testsuite/lib/target-supports.exp | 29 ++++-
7 files changed, 160 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 212f288e3c2..430eb25459a 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -230,6 +230,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_SVE2_SHA3, "__ARM_FEATURE_SVE2_SHA3", pfile);
aarch64_def_or_undef (TARGET_SVE2_SM4, "__ARM_FEATURE_SVE2_SM4", pfile);
aarch64_def_or_undef (TARGET_SVE2p1, "__ARM_FEATURE_SVE2p1", pfile);
+ aarch64_def_or_undef (TARGET_SVE2p2, "__ARM_FEATURE_SVE2p2", pfile);
aarch64_def_or_undef (TARGET_LSE, "__ARM_FEATURE_ATOMICS", pfile);
aarch64_def_or_undef (TARGET_AES, "__ARM_FEATURE_AES", pfile);
@@ -310,6 +311,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
"__ARM_FEATURE_SME2p1", pfile);
+ aarch64_def_or_undef (TARGET_SME2p2, "__ARM_FEATURE_SME2p2", pfile);
aarch64_def_or_undef (TARGET_FAMINMAX, "__ARM_FEATURE_FAMINMAX", pfile);
aarch64_def_or_undef (TARGET_PCDPHINT, "__ARM_FEATURE_PCDPHINT", pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_TMOP),
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index cfebc3fc572..821dfb25d66 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -327,6 +327,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
/* SVE2p1 instructions, enabled through +sve2p1. */
#define TARGET_SVE2p1 AARCH64_HAVE_ISA (SVE2p1)
+/* SVE2p2 instructions, enabled through +sve2p2. */
+#define TARGET_SVE2p2 AARCH64_HAVE_ISA (SVE2p2)
+
/* SME instructions, enabled through +sme. Note that this does not
imply anything about the state of PSTATE.SM; instructions that require
SME and streaming mode should use TARGET_STREAMING instead. */
@@ -357,6 +360,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
/* SME2 instructions, enabled through +sme2. */
#define TARGET_SME2 AARCH64_HAVE_ISA (SME2)
+/* SME2p2 instructions, enabled through +sme2p2. */
+#define TARGET_SME2p2 AARCH64_HAVE_ISA (SME2p2)
+
/* Same with streaming mode enabled. */
#define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 70a64a6c0ed..cfceef91fbb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -502,7 +502,7 @@
;; Q registers and is equivalent to "simd".
(define_enum "arches" [any rcpc8_4 fp fp_q base_simd nobase_simd
- simd nosimd sve fp16 sme cssc])
+ simd nosimd sve fp16 sme cssc sve2p2_or_sme2p2])
(define_enum_attr "arch" "arches" (const_string "any"))
@@ -581,7 +581,10 @@
(match_test "TARGET_SVE"))
(and (eq_attr "arch" "sme")
- (match_test "TARGET_SME"))))
+ (match_test "TARGET_SME"))
+
+ (and (eq_attr "arch" "sve2p2_or_sme2p2")
+ (match_test "TARGET_SVE2p2_OR_SME2p2"))))
(const_string "yes")
(const_string "no")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1dfa708df7b..46fb8ba7a20 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23534,6 +23534,8 @@ Enable SVE2 aes instructions. This also enables SVE2
instructions.
Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
@item sve2p1
Enable SVE2.1 instructions. This also enables SVE2 instructions.
+@item sve2p2
+Enable SVE2.2 instructions. This also enables SVE2 and SVE2.1 instructions.
@item tme
Enable the Transactional Memory Extension.
@item i8mm
@@ -23600,6 +23602,9 @@ instructions.
@item sme2p1
Enable the Scalable Matrix Extension version 2.1. This also enables SME2
instructions.
+@item sme2p2
+Enable the Scalable Matrix Extension version 2.2. This also enables SME2
+and SME2.1 instructions.
@item fcma
Enable the complex number SIMD extensions.
@item jscvt
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_3.c
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_3.c
index f1f70ed7b5c..9c96249050d 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_3.c
@@ -32,6 +32,10 @@
#error "__ARM_FEATURE_SVE2p1 is defined but should not be!"
#endif
+#ifdef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is defined but should not be!"
+#endif
+
#pragma GCC push_options
#pragma GCC target ("arch=armv8.2-a+sve")
@@ -63,6 +67,10 @@
#error "__ARM_FEATURE_SVE2p1 is defined but should not be!"
#endif
+#ifdef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is defined but should not be!"
+#endif
+
#pragma GCC pop_options
#pragma GCC push_options
@@ -96,6 +104,10 @@
#error "__ARM_FEATURE_SVE2p1 is defined but should not be!"
#endif
+#ifdef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is defined but should not be!"
+#endif
+
#pragma GCC pop_options
#pragma GCC push_options
@@ -287,6 +299,47 @@
#error "__ARM_FEATURE_SVE2p1 is not defined but should be!"
#endif
+#ifdef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is defined but should not be!"
+#endif
+
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv9-a+sve2p2")
+
+#ifndef __ARM_FEATURE_SVE
+#error "__ARM_FEATURE_SVE is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2
+#error "__ARM_FEATURE_SVE2 is not defined but should be!"
+#endif
+
+#ifdef __ARM_FEATURE_SVE2_AES
+#error "__ARM_FEATURE_SVE2_AES is defined but should not be!"
+#endif
+
+#ifdef __ARM_FEATURE_SVE2_BITPERM
+#error "__ARM_FEATURE_SVE2_BITPERM is defined but should not be!"
+#endif
+
+#ifdef __ARM_FEATURE_SVE2_SHA3
+#error "__ARM_FEATURE_SVE2_SHA3 is defined but should not be!"
+#endif
+
+#ifdef __ARM_FEATURE_SVE2_SM4
+#error "__ARM_FEATURE_SVE2_SM4 is defined but should not be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2p1
+#error "__ARM_FEATURE_SVE2p1 is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is not defined but should be!"
+#endif
+
#pragma GCC pop_options
#pragma GCC push_options
@@ -320,6 +373,48 @@
#error "__ARM_FEATURE_SVE2p1 is not defined but should be!"
#endif
+#ifdef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is defined but should not be!"
+#endif
+
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target
("arch=armv9-a+sve2-aes+sve2-bitperm+sve2-sha3+sve2-sm4+sve2p1+sve2p2")
+
+#ifndef __ARM_FEATURE_SVE
+#error "__ARM_FEATURE_SVE is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2
+#error "__ARM_FEATURE_SVE2 is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2_AES
+#error "__ARM_FEATURE_SVE2_AES is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2_BITPERM
+#error "__ARM_FEATURE_SVE2_BITPERM is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2_SHA3
+#error "__ARM_FEATURE_SVE2_SHA3 is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2_SM4
+#error "__ARM_FEATURE_SVE2_SM4 is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2p1
+#error "__ARM_FEATURE_SVE2p1 is not defined but should be!"
+#endif
+
+#ifndef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is not defined but should be!"
+#endif
+
+
#pragma GCC push_options
#pragma GCC target ("general-regs-only")
@@ -351,6 +446,11 @@
#error "__ARM_FEATURE_SVE2p1 is defined but should not be!"
#endif
+#ifdef __ARM_FEATURE_SVE2p2
+#error "__ARM_FEATURE_SVE2p2 is defined but should not be!"
+#endif
+
+
#pragma GCC pop_options
#pragma GCC pop_options
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index d3630de955d..d7976e3f1b1 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -218,6 +218,20 @@
#error Foo
#endif
+#pragma GCC target "+nothing+sve2+sme2p2"
+#ifndef __ARM_FEATURE_SME
+#error Foo
+#endif
+#ifndef __ARM_FEATURE_SME2
+#error Foo
+#endif
+#ifndef __ARM_FEATURE_SME2p1
+#error Foo
+#endif
+#ifndef __ARM_FEATURE_SME2p2
+#error Foo
+#endif
+
#pragma GCC target "+nothing+sve2+sme-mop4"
#ifndef __ARM_FEATURE_SME_MOP4
#error "__ARM_FEATURE_SME_MOP4 not defined"
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 384ec440f65..f0def086a30 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6652,6 +6652,23 @@ proc check_effective_target_aarch64_sve2p1_hw { } {
}]
}
+# Return true if this is an AArch64 target that can run SVE2.2 code.
+
+proc check_effective_target_aarch64_sve2p2_hw { } {
+ if { ![istarget aarch64*-*-*] } {
+ return 0
+ }
+ return [check_runtime aarch64_sve2p2_hw_available {
+ #pragma GCC target "+sve2p2"
+ int
+ main (void)
+ {
+ asm volatile ("compact z0.b, p0, z1.b");
+ return 0;
+ }
+ }]
+}
+
# Return true if this is an AArch64 target that can run SVE code and
# if its SVE vectors have exactly BITS bits.
@@ -12731,7 +12748,7 @@ set exts {
# archiecture for SME and the features that require it.
set exts_sve2 {
"sme-f8f16" "sme-f8f32"
- "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1"
+ "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
"ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale"
"sme-tmop" "ssve-bitperm"
}
@@ -12784,6 +12801,16 @@ proc check_effective_target_aarch64_asm_sve2p1_ok { } {
}
}
+proc check_effective_target_aarch64_asm_sve2p2_ok { } {
+ if { [istarget aarch64*-*-*] } {
+ return [check_no_compiler_messages aarch64_sve2p2_assembler object {
+ __asm__ (".arch_extension sve2p2; compact z0.b,p0,z1.b");
+ } "-march=armv8-a+sve2p2"]
+ } else {
+ return 0
+ }
+}
+
proc check_effective_target_aarch64_small { } {
if { [istarget aarch64*-*-*] } {
return [check_no_compiler_messages aarch64_small object {
--
2.43.0
