The load_multiple_sequence function already supports ldm_case=5 to handle
memory references with arbitrary ARM-encodable constant offsets (via
const_ok_for_arm). However, the corresponding store path in
store_multiple_sequence lacked this capability, even though gen_stm_seq
was prepared to handle stm_case=5.
The change adds a check similar to load_multiple_sequence: when the
offset is not zero but can be encoded as an ARM immediate (using
const_ok_for_arm), we now return stm_case = 5. This enables the
generation of add+stm sequences for store operations, improving
code size and maintaining consistency between load and store
optimizations.
gcc/ChangeLog:
* config/arm/arm.c (store_multiple_sequence): Add support for
stm_case=5 using const_ok_for_arm to check offset encodability.
Signed-off-by: tanshanshan <[email protected]>
---
gcc/config/arm/arm.cc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 0a1f6612d07..5861849daae 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -14907,6 +14907,9 @@ store_multiple_sequence (rtx *operands, int nops, int
nops_total,
stm_case = 3; /* stmda */
else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
stm_case = 4; /* stmdb */
+ else if (const_ok_for_arm (unsorted_offsets[order[0]])
+ || const_ok_for_arm (-unsorted_offsets[order[0]]))
+ stm_case = 5;
else
return 0;
--
2.43.0
