Hi Nikola, > This patch introduces a vector cost model for the Spacemit-X60 core. > > The model is LMUL-aware, based on measurements showing that vector instruction > latency and throughput vary significantly with LMUL, so the cost > model distinguishes between m1/m2/m4/m8 cases. > > To keep the machine description manageable, a new 'vector_lmul' > attribute is introduced to map RVV modes to their corresponding LMUL > values. The costs are based on llvm-mca performance simulations > and microbenchmarks, with additional stress tests used to validate > and adjust individual instruction types.
We have -madjust-lmul-cost which is undocumented but should help with what you're trying to do. With it it shouldn't be necessary to add explicit LMUL handling. > (define_insn_reservation "spacemit_x60_vec_fwred_m8" 256 > (and (eq_attr "tune" "spacemit_x60") > (and (eq_attr "type" "vfwredo,vfwredu") > (eq_attr "vector_lmul" "m8"))) > "spacemit_x60_vxu0*256") Reserving the unit for 256 cycles will lead to crazy build times (building the automaton will take forever). It's better to keep the latency and clamp the number of cycles the unit is reserved to a reasonable small value, like 8 or 10. -- Regards Robin
