On Friday 6 February 2026 21:12:30 Central European Standard Time Jérôme Pouiller wrote: > Some chips (such as SiWx917 from Silicon Labs) have slow data bus > access. The -mslow-flash-data option generates appropriate code for > these chips by disabling literal pools. However, the current > implementation completely prevents TLS (Thread Local Storage) variables > from working, since ARM does not provide relocations to encode TLS > variables directly into instructions - they require literal pools. > > This change relaxes the -mslow-flash-data constraint to allow literal > pools specifically for TLS accesses. While this results in slower TLS > access (hence a warning is emitted), it is preferable to a hard error > that prevents TLS usage entirely. > > With -mpure-code, literal pools remain completely disabled and TLS > access still results in an error.
Maybe it's also worth to mention I have also tested -mslow-flash-data on regular Cortex-M [1], without the limitations we have on SiWx917. I have observed slightly improved results[2]: ~5-8%. I didn't take time to analyze this result, but it may interest other people. [1]: the exact target I used is Silabs EFR32xG29 with Cortex-M33 @78MHz [2]: using the kernel benchmark of Zephyr OS -- Jérôme Pouiller
