From: Lino Hsing-Yu Peng <[email protected]>

Add initial ISA-level for Zvfofp8min extension.

gcc/ChangeLog:

        * common/config/riscv/riscv-common.cc: Add zvfofp8min support.
        * config/riscv/riscv-ext.def: Add zvfofp8min entry.
        * config/riscv/riscv-ext.opt: Add zvfofp8min option.
        * config/riscv/riscv-vector-builtins.cc: Require zvfofp8min.
        * config/riscv/riscv-vector-builtins.h: Add zvfofp8min handling.
        * doc/riscv-ext.texi: Document the new extension.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/arch-61.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 ++
 gcc/config/riscv/riscv-ext.def            | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt            |  3 ++-
 gcc/config/riscv/riscv-vector-builtins.cc |  2 ++
 gcc/config/riscv/riscv-vector-builtins.h  |  7 +++++++
 gcc/doc/riscv-ext.texi                    |  4 ++++
 gcc/testsuite/gcc.target/riscv/arch-61.c  |  5 +++++
 7 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-61.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5d3d37c7a7b..8c4b3c4dd4b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1485,6 +1485,8 @@ static const riscv_extra_ext_flag_table_t 
riscv_extra_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16),
   RISCV_EXT_FLAG_ENTRY ("zvfhmin",  x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16),
   RISCV_EXT_FLAG_ENTRY ("zvfh",     x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16),
+  RISCV_EXT_FLAG_ENTRY ("zvfofp8min", x_riscv_vector_elen_flags,
+                       MASK_VECTOR_ELEN_FP_32),
 
   RISCV_EXT_FLAG_ENTRY ("xtheadvector",  x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_32),
   RISCV_EXT_FLAG_ENTRY ("xtheadvector",  x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_64),
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 1621e81b011..860ee34796b 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1156,6 +1156,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ zvfofp8min,
+  /* UPPERCASE_NAME */ ZVFOFP8MIN,
+  /* FULL_NAME */ "Vector FP8 minimum extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zve32f"}),
+  /* SUPPORTED_VERSIONS */ ({{0, 2}}),
+  /* FLAG_GROUP */ zvf,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ zvfbfwma,
   /* UPPERCASE_NAME */ ZVFBFWMA,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 18402ea97c7..6725175f903 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -264,6 +264,8 @@ Mask(ZVE64X) Var(riscv_zve_subext)
 
 Mask(ZVFBFMIN) Var(riscv_zvf_subext)
 
+Mask(ZVFOFP8MIN) Var(riscv_zvf_subext)
+
 Mask(ZVFBFWMA) Var(riscv_zvf_subext)
 
 Mask(ZVFH) Var(riscv_zvf_subext)
@@ -471,4 +473,3 @@ Mask(XANDESVPACKFPH) Var(riscv_xandes_subext)
 Mask(XANDESVDOT) Var(riscv_xandes_subext)
 
 Mask(XSMTVDOT) Var(riscv_xsmt_subext)
-
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
b/gcc/config/riscv/riscv-vector-builtins.cc
index 92f343c0044..5892ae5e466 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3654,6 +3654,8 @@ get_builtin_partition (required_ext ext, const 
function_instance &instance)
       return RVV_PARTITION_ZVFBFMIN;
     case ZVFBFWMA_EXT:
       return RVV_PARTITION_ZVFBFWMA;
+    case ZVFOFP8MIN_EXT:
+      return RVV_PARTITION_ZVFOFP8MIN;
     case XSFVQMACCQOQ_EXT:
       return RVV_PARTITION_XSFVQMACCQOQ;
     case XSFVQMACCDOD_EXT:
diff --git a/gcc/config/riscv/riscv-vector-builtins.h 
b/gcc/config/riscv/riscv-vector-builtins.h
index d5fe0cd7a22..224a90c0b26 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -110,6 +110,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5;
 #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5)       /* Require TARGET_MIN_VLEN >= 
64.  */
 #define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32.  */
 #define RVV_REQUIRE_ELEN_BF_16 (1 << 7) /* Require BF16.  */
+#define RVV_REQUIRE_ZVFOFP8MIN (1 << 8) /* Require ZVFOFP8MIN extension.  */
 
 /* Enumerates the required extensions.  */
 enum required_ext
@@ -129,6 +130,7 @@ enum required_ext
   ZVKSH_EXT,           /* Crypto vector Zvksh sub-ext */
   ZVFBFMIN_EXT,                /* Zvfbfmin extension */
   ZVFBFWMA_EXT,                /* Zvfbfwma extension */
+  ZVFOFP8MIN_EXT,      /* Zvfofp8min extension */
   XSFVQMACCQOQ_EXT,    /* XSFVQMACCQOQ extension */
   XSFVQMACCDOD_EXT,    /* XSFVQMACCDOD extension */
   XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */
@@ -159,6 +161,7 @@ enum rvv_builtin_partition
   RVV_PARTITION_ZVFBFWMA,
   RVV_PARTITION_ZVFHMIN,
   RVV_PARTITION_ZVFH,
+  RVV_PARTITION_ZVFOFP8MIN,
   RVV_PARTITION_XSFVQMACCQOQ,
   RVV_PARTITION_XSFVQMACCDOD,
   RVV_PARTITION_XSFVFNRCLIPXFQF,
@@ -211,6 +214,8 @@ static inline const char * required_ext_to_isa_name (enum 
required_ext required)
       return "zvfbfmin";
     case ZVFBFWMA_EXT:
       return "zvfbfwma";
+    case ZVFOFP8MIN_EXT:
+      return "zvfofp8min";
     case XSFVQMACCQOQ_EXT:
       return "xsfvqmaccqoq";
     case XSFVQMACCDOD_EXT:
@@ -266,6 +271,8 @@ static inline bool required_extensions_specified (enum 
required_ext required)
       return TARGET_ZVFBFMIN;
     case ZVFBFWMA_EXT:
       return TARGET_ZVFBFWMA;
+    case ZVFOFP8MIN_EXT:
+      return TARGET_ZVFOFP8MIN;
     case XSFVQMACCQOQ_EXT:
       return TARGET_XSFVQMACCQOQ;
     case XSFVQMACCDOD_EXT:
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 36b4dff31ff..1511c8be993 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -334,6 +334,10 @@
 @tab 1.0
 @tab Vector BF16 converts extension
 
+@item @samp{zvfofp8min}
+@tab 0.2
+@tab Vector FP8 minimum extension
+
 @item @samp{zvfbfwma}
 @tab 1.0
 @tab Vector BF16 widening multiply/add extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-61.c 
b/gcc/testsuite/gcc.target/riscv/arch-61.c
new file mode 100644
index 00000000000..921a43cebd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-61.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvfofp8min -mabi=lp64" } */
+int
+foo ()
+{}
-- 
2.34.1

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