Hi,
This fixes a latent bug on rv32 after the lra patch for PR123381.
Jeff ran the test through his tester and found exactly one bit of fallout - on
riscv32:
We have those _lra insn_and_splits
(define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
[(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
(match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
(clobber (match_scratch:P 2 "=&r,&r,X"))]
where the clobber constraint for the third alternative is 'X'.
This is supposed to express that we accept anything because we don't
need the scratch for that alternative anyway.
However, in mask_gather_load_run-11.c we create a mem
(insn 302 228 218 (parallel [
(set (reg:RVVMF8BI 124 v28 [orig:214 mask__62.15 ] [214])
(reg:RVVMF8BI 120 v24 [orig:354 MEM <vector(16) long long int>
[(int64_t *)cond_32(D) + 768B] ] [354]))
(clobber (mem/c:SI (plus:SI (reg/f:SI 2 sp)
(const_int 12 [0xc])) [3 %sfp+-324 S4 A32]))
that match_scratch does not handle, so we never split the insn.
This patch changes the constraint to 'r', this should work as we don't
make use of it anyway.
Regtested on rv64gcv_zvl512b.
Regards
Robin
gcc/ChangeLog:
* config/riscv/vector.md: Change 'X' to 'r' in _lra insns.
---
gcc/config/riscv/vector.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 219ecdac68b..45be9e6fe17 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1341,7 +1341,7 @@ (define_expand "@mov<VB:mode><P:mode>_lra"
(define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
[(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
(match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
- (clobber (match_scratch:P 2 "=&r,&r,X"))]
+ (clobber (match_scratch:P 2 "=&r,&r,r"))]
"TARGET_VECTOR && (lra_in_progress || reload_completed)"
"#"
"&& reload_completed"
@@ -1363,7 +1363,7 @@ (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
(define_insn_and_split "*mov<VB:mode><P:mode>_lra"
[(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
(match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
- (clobber (match_scratch:P 2 "=&r,&r,X"))]
+ (clobber (match_scratch:P 2 "=&r,&r,r"))]
"TARGET_VECTOR && (lra_in_progress || reload_completed)"
"#"
"&& reload_completed"
@@ -1491,7 +1491,7 @@ (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
(define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
(match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
- (clobber (match_scratch:P 2 "=&r,&r,X"))]
+ (clobber (match_scratch:P 2 "=&r,&r,r"))]
"TARGET_VECTOR && (lra_in_progress || reload_completed)
&& (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
|| register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
--
2.53.0
