Re: [PATCH] i386: Fix up *avx512f_load_mask for -masm=intel [PR124335]

[Hongtao Liu]

On Wed, Mar 4, 2026 at 8:18 AM Andrew Pinski
<andrew.pin...@oss.qualcomm.com> wrote:
>
> On Tue, Mar 3, 2026 at 12:18 AM Jakub Jelinek <ja...@redhat.com> wrote:
> >
> > Hi!
> >
> > The Intel syntax part is missing % before 3, so it always prints {3}
> > rather than {k1} or similar.
> >
> > Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
> > trunk?
>
> This testcase fails with binutils 2.35:
vmovw is supported in binutils 2.38 and later, need
/* { dg-require-effective-target avx512fp16 } */ to avoid errors.

> ```
> /tmp/ccf20y5C.s:20: Error: no such instruction: `vmovw xmm0,WORD PTR 
> .LC0[rip]'
> /tmp/ccf20y5C.s:21: Error: no such instruction: `vmovw WORD PTR [rbp-18],xmm0'
> /tmp/ccf20y5C.s:22: Error: no such instruction: `vmovw xmm0,WORD PTR [rbp-18]'
> /tmp/ccf20y5C.s:23: Error: no such instruction: `vmovw WORD PTR [rbp-20],xmm0'
> /tmp/ccf20y5C.s:24: Error: no such instruction: `vmovw xmm0,WORD PTR [rbp-18]'
> /tmp/ccf20y5C.s:25: Error: no such instruction: `vmovw WORD PTR [rbp-22],xmm0'
> /tmp/ccf20y5C.s:26: Error: no such instruction: `vmovw xmm0,WORD PTR [rbp-18]'
> /tmp/ccf20y5C.s:27: Error: no such instruction: `vmovw WORD PTR [rbp-24],xmm0'
> /tmp/ccf20y5C.s:28: Error: no such instruction: `vmovw xmm0,WORD PTR [rbp-18]'
> /tmp/ccf20y5C.s:29: Error: no such instruction: `vmovw WORD PTR [rbp-26],xmm0'
> /tmp/ccf20y5C.s:30: Error: no such instruction: `vmovw xmm0,WORD PTR [rbp-18]'
> ```
>
> Thanks,
> Andrew Pinski
>
>
> >
> > 2026-03-03  Jakub Jelinek  <ja...@redhat.com>
> >
> >         PR target/124335
> >         * config/i386/sse.md (*avx512f_load<mode>_mask): Use %{%3%} instead 
> > of
> >         %{3%} for -masm=intel syntax.
> >
> >         * gcc.target/i386/avx512fp16-pr124335.c: New test.
> >
> > --- gcc/config/i386/sse.md.jj   2026-03-02 15:42:37.301524399 +0100
> > +++ gcc/config/i386/sse.md      2026-03-02 20:08:37.596847221 +0100
> > @@ -1744,7 +1744,7 @@ (define_insn "*avx512f_load<mode>_mask"
> >           (match_operand:<ssevecmode> 4 "const0_operand")
> >           (const_int 1)))]
> >    "TARGET_AVX512F"
> > -  "vmov<ssescalarmodesuffix>\t{%1, %0%{%3%}%N2|%0%{3%}%N2, %1}"
> > +  "vmov<ssescalarmodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
> >    [(set_attr "type" "ssemov")
> >     (set_attr "prefix" "evex")
> >     (set_attr "memory" "load")
> > --- gcc/testsuite/gcc.target/i386/avx512fp16-pr124335.c.jj      2026-03-02 
> > 20:15:26.543007388 +0100
> > +++ gcc/testsuite/gcc.target/i386/avx512fp16-pr124335.c 2026-03-02 
> > 20:17:58.529465343 +0100
> > @@ -0,0 +1,13 @@
> > +/* PR target/124335 */
> > +/* { dg-do assemble } */
> > +/* { dg-require-effective-target masm_intel } */
> > +/* { dg-options "-mavx512fp16 -masm=intel" } */
> > +/* { dg-require-effective-target avx512bw } */
> > +
> > +#include <x86intrin.h>
> > +
> > +__m128h
> > +foo (_Float16 const *x, __mmask8 y)
> > +{
> > +  return _mm_maskz_load_sh (y, x);
> > +}
> >
> >         Jakub
> >



-- 
BR,
Hongtao