> -----Original Message-----
> From: Jakub Jelinek <[email protected]>
> Sent: Thursday, March 5, 2026 4:34 PM
> To: Uros Bizjak <[email protected]>; Liu, Hongtao <[email protected]>
> Cc: [email protected]
> Subject: [PATCH] i386: Fix up last -masm=intel operand of vcvthf82ph
> [PR124349]
>
> Hi!
>
> gas expects for this instruction
> vcvthf82ph xmm30, QWORD PTR [r9]
> vcvthf82ph ymm30, XMMWORD PTR [r9]
> vcvthf82ph zmm30, YMMWORD PTR [r9]
> i.e. the memory size is half of the dest register size.
> We currently emit it for the last 2 forms but emit XMMWORD PTR for the first
> one too. So, we need %q1 for V8HF and for V16HF/V32HF can either use
> just %1 or %x1/%t1. There is no define_mode_attr that would provide those,
> so I've added one just for this insn.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
Ok.
>
> 2026-03-05 Jakub Jelinek <[email protected]>
>
> PR target/124349
> * config/i386/sse.md (iptrssebvec_2): New define_mode_attr.
> (cvthf82ph<mode><mask_name>): Use it for -masm=intel input
> operand.
>
> * gcc.target/i386/avx10_2-pr124349-2.c: New test.
>
> --- gcc/config/i386/sse.md.jj 2026-03-04 09:38:22.303804750 +0100
> +++ gcc/config/i386/sse.md 2026-03-04 11:19:43.379897634 +0100
> @@ -32450,6 +32450,9 @@ (define_insn "vcvt<convertfp8_pack><mode
> (define_mode_attr ssebvecmode_2
> [(V8HF "V16QI") (V16HF "V16QI") (V32HF "V32QI")])
>
> +(define_mode_attr iptrssebvec_2
> + [(V8HF "q") (V16HF "") (V32HF "")])
> +
> (define_int_iterator UNSPEC_VCVTBIASPH2FP8_PACK
> [UNSPEC_VCVTBIASPH2BF8 UNSPEC_VCVTBIASPH2BF8S
> UNSPEC_VCVTBIASPH2HF8 UNSPEC_VCVTBIASPH2HF8S]) @@ -32626,7
> +32629,7 @@ (define_insn "vcvthf82ph<mode><mask_name
> [(match_operand:<ssebvecmode_2> 1 "nonimmediate_operand"
> "vm")]
> UNSPEC_VCVTHF82PH))]
> "TARGET_AVX10_2"
> - "vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> +
> "vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptrssebv
> ec_2>1}"
> [(set_attr "prefix" "evex")])
>
> (define_int_iterator VPDPWPROD
> --- gcc/testsuite/gcc.target/i386/avx10_2-pr124349-2.c.jj 2026-03-04
> 11:40:04.022251177 +0100
> +++ gcc/testsuite/gcc.target/i386/avx10_2-pr124349-2.c 2026-03-04
> 11:39:45.490564632 +0100
> @@ -0,0 +1,41 @@
> +/* PR target/124349 */
> +/* { dg-do assemble { target { avx10_2 && masm_intel } } } */
> +/* { dg-options "-O2 -mavx10.2 -masm=intel" } */
> +
> +#include <x86intrin.h>
> +
> +__m128h
> +foo (__m128i *p)
> +{
> + return _mm_cvthf8_ph (*p);
> +}
> +
> +__m128h
> +bar (__m128i *p, __m128h w, __mmask8 u) {
> + return _mm_mask_cvthf8_ph (w, u, *p); }
> +
> +__m256h
> +baz (__m128i *p)
> +{
> + return _mm256_cvthf8_ph (*p);
> +}
> +
> +__m256h
> +qux (__m128i *p, __m256h w, __mmask16 u) {
> + return _mm256_mask_cvthf8_ph (w, u, *p); }
> +
> +__m512h
> +fred (__m256i *p)
> +{
> + return _mm512_cvthf8_ph (*p);
> +}
> +
> +__m512h
> +corge (__m256i *p, __m512h w, __mmask32 u) {
> + return _mm512_mask_cvthf8_ph (w, u, *p); }
>
> Jakub
