This patch adds support for new -march feature options
corresponding to 2025 architecture extensions.
* +poe2
* +tlbid
* +tev
* +gcie
* +mpamv2
* +lscp
* +mops-go
* +sve2p3
* +sme2p3
* +f16f32dot
* +sve-b16mm
* +mtetc
Regression tested on aarch64-none-elf and aarch64-linux-gnu
and found no regressions.
Ok for master?
Regards,
Srinath
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (poe2):
New CLI extension option.
(tev): Likewise.
(tlbid): Likewise.
(gcie): Likewise.
(mpamv2): Likewise.
(lscp): Likewise.
(mops-go): Likewise.
(sve2p3): Likewise.
(sme2p3): Likewise.
(f16f32dot): Likewise.
(sve-b16mm): Likewise.
(mtetc): Likewise.
* doc/invoke.texi (poe2): Document option.
(tev): Likewise.
(tlbid): Likewise.
(gcie): Likewise.
(mpamv2): Likewise.
(lscp): Likewise.
(mops-go): Likewise.
(sve2p3): Likewise.
(sme2p3): Likewise.
(f16f32dot): Likewise.
(sve-b16mm): Likewise.
(mtetc): Likewise.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_aarch64_poe2_tev_support_ok): Add new target
check.
* gcc.target/aarch64/asm-arch-features-2025.c: New test.
---
.../aarch64/aarch64-option-extensions.def | 24 +++++++++++++++++
gcc/doc/invoke.texi | 26 +++++++++++++++++++
.../aarch64/asm-arch-features-2025.c | 11 ++++++++
gcc/testsuite/lib/target-supports.exp | 10 +++++++
4 files changed, 71 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
b/gcc/config/aarch64/aarch64-option-extensions.def
index b5e4b062bed..be25098e4f0 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -351,6 +351,30 @@ AARCH64_OPT_EXTENSION("pcdphint", PCDPHINT, (), (), (), "")
AARCH64_OPT_EXTENSION("pops", PoPS, (), (), (), "")
+AARCH64_OPT_EXTENSION("poe2", POE2, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("tev", TEV, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("tlbid", TLBID, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("gcie", GCIE, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("mpamv2", MPAMv2, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("lscp", LSCP, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("mops-go", MOPS_GO, (MOPS, MEMTAG), (), (), "")
+
+AARCH64_OPT_EXTENSION("sve2p3", SVE2p3, (SVE2p2), (), (), "")
+
+AARCH64_OPT_EXTENSION("sme2p3", SME2p3, (SME2p2), (), (), "")
+
+AARCH64_OPT_EXTENSION("f16f32dot", F16F32DOT, (SIMD, F16), (), (), "")
+
+AARCH64_OPT_EXTENSION("sve-b16mm", SVE_B16MM, (SVE), (), (), "")
+
+AARCH64_OPT_EXTENSION("mtetc", MTETC, (MEMTAG), (), (), "")
+
#undef AARCH64_OPT_FMV_EXTENSION
#undef AARCH64_OPT_EXTENSION
#undef AARCH64_OPT_EXTENSION_ALIAS
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a93aa214565..ffc60cc3ecf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21946,6 +21946,32 @@ Enable the SVE non-widening brain floating-point
(@code{bf16}) extension.
This only has an effect when @code{sve2} or @code{sme2} are also enabled.
@item sve-bfscale
Enable the SVE_BFSCALE extension.
+@item poe2
+Enable the Permission Overlays Extension 2.
+@item tev
+Enable the TIndex Exception-like Vector Extension.
+@item tlbid
+Enable the TLBI Domains Extension.
+@item gcie
+Enable the GICv5 (Generic Interrupt Controller) CPU Interface Extension.
+@item mpamv2
+Enable MPAMv2 system registers.
+@item lscp
+Enable the load acquire and store release pair extension.
+@item mops-go
+Enable tag only variants of MOPS instructions and this also enables @code{mops}
+and @code{memtag}.
+@item sve2p3
+Enable SVE2.3 and this also enables @code{sve2p2}.
+@item sme2p3
+Enable SME2.3 and this also enables @code{sme2p2}.
+@item f16f32dot
+Enable Armv9.7 f16f32dot instructions and this also enables @code{simd}
+and @code{f16}.
+@item sve-b16mm
+Enable the SVE B16MM Extension and this also enables @code{sve}.
+@item mtetc
+Enable Data cache tag block operations and this also enables @code{memtag}.
@end table
Feature @option{crypto} implies @option{aes}, @option{sha2}, and @option{simd},
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
b/gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
new file mode 100644
index 00000000000..16c7fedacb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
@@ -0,0 +1,11 @@
+/* { dg-do assemble { target elf } } */
+/* { dg-require-effective-target aarch64_arch2025_support_ok } */
+/* { dg-additional-options
"-march=armv8-a+poe2+tev+tlbid+mpamv2+gcie+lscp+mops-go+sve2p3+sme2p3+f16f32dot+sve-b16mm+mtetc"
} */
+/* Ensure above -march options are passed to the assembler and that the test
+ runs only when those features are supported by the assembler. */
+
+int
+arch_2025 ()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3f428ad5817..62328bb5c7e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12766,6 +12766,16 @@ proc check_effective_target_aarch64_sysreg_guarding_ok
{ } {
}
}
+proc check_effective_target_aarch64_arch2025_support_ok { } {
+ if { [istarget aarch64*-*-*] && [check_effective_target_elf] } {
+ return [check_no_compiler_messages aarch64_assembler object {
+ __asm__ ("tchangef x0, x1");
+ }
"-march=armv8-a+poe2+tev+tlbid+mpamv2+gcie+lscp+mops-go+sve2p3+sme2p3+f16f32dot+sve-b16mm+mtetc"]
+ } else {
+ return 0
+ }
+}
+
proc check_effective_target_aarch64_asm_sve2p1_ok { } {
if { [istarget aarch64*-*-*] } {
return [check_no_compiler_messages aarch64_sve2p1_assembler object {
--
2.25.1
