From: Pan Li <[email protected]>
Add asm dump check and run test for vec_duplicate + vmsgt.vv
combine to vmsgt.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
for vmsgt.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c: New test.
Signed-off-by: Pan Li <[email protected]>
---
.../riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx_binary.h | 1 +
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 ++++++++++++++++++
.../rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c | 15 ++
.../rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c | 15 ++
.../rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c | 15 ++
.../rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c | 15 ++
18 files changed, 209 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 683e7cebb28..b27bb338ee2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 07dcc2ec7e5..bc9b80f67cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index b30fe640d21..9b8de9cfea1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -34,3 +34,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 01b426afbfb..2e6ec208858 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 532e1884aea..2d8263e0487 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 5ed2711c032..bacf86c296f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index b494695098e..e32719036d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 8fdee21f931..aee6563b07b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 841b88e4c2c..2371d3fe250 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e80fdcc7357..4b343f66aec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 548a3218e7f..5b8b853c320 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index eb10722f2d2..407261aad74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vmsne.vx} } } */
/* { dg-final { scan-assembler-not {vmslt.vx} } } */
/* { dg-final { scan-assembler-not {vmsle.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgt.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index ff6b7f6542d..2291d9e9601 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -406,6 +406,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \
DEF_VX_BINARY_CASE_0_WRAP(T, <, lt) \
DEF_VX_BINARY_CASE_0_WRAP(T, <=, le) \
+ DEF_VX_BINARY_CASE_0_WRAP(T, >, gt) \
DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \
DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \
DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 952c8b49ecd..3cccd65b749 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -7110,4 +7110,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, gtu)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, gt)[][3][N] =
+{
+ {
+ { 127 },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 127, 127, 127, 127,
+ -128, -128, -128, -128,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { -1 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -2, -2, -2, -2,
+ -128, -128, -128, -128,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, gt)[][3][N] =
+{
+ {
+ { 32767 },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 32767, 32767, 32767, 32767,
+ -32768, -32768, -32768, -32768,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { -1 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -2, -2, -2, -2,
+ -32768, -32768, -32768, -32768,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, gt)[][3][N] =
+{
+ {
+ { 2147483647 },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { -1 },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -2, -2, -2, -2,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, gt)[][3][N] =
+{
+ {
+ { 9223372036854775807ll },
+ {
+ 0, 0,
0, 0,
+ -1, -1,
-1, -1,
+ 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll, 9223372036854775807ll,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ { -1 },
+ {
+ 0, 0,
0, 0,
+ 1, 1,
1, 1,
+ -2, -2,
-2, -2,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c
new file mode 100644
index 00000000000..0c5c8bbe63d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME gt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c
new file mode 100644
index 00000000000..239f029675b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME gt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c
new file mode 100644
index 00000000000..fbc59bf6e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME gt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c
new file mode 100644
index 00000000000..1fe1dbeaf29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME gt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
--
2.43.0
