On Mon, May 11, 2026 at 05:48:53PM +0530, jeevitha wrote: > Hi All, > > This patch depends on the smul/umul pattern fix. This will be upstreamed > after the above fix is upstreamed. These changes have been bootstrapped > and regression tested on powerpc64le-linux. Is this okay for trunk?
This looks ok for the trunk, and after a burn in period, you can back port it to the older active branches. For the store asms, it might make sense to add : "memory" to indicate memory is also changed. In theory asm volatile should be sufficient, but it probably doesn't hurt to indicate memory is also modified. Originally in _AMO_LD_CMPSWP, I was going to suggest maybe using some other gprs than r8-r10, since they are for arguments. But we don't have any suitable volatile registers to use. > > Changes from V1: > * Incorporated wording suggestions. > * Renamed mode iterators to VIMulH and VIArith for better clarity. > * Removed extra blank line in vsx_simd-*.c test case. > * Replaced unspec with proper smul_highpart and umul_highpart RTL > codes for multiply-high patterns. > * Added * prefix to internal patterns for vsx_add, vsx_sub, altivec_add, > altivec_sub, altivec_smul and altivec_umul. > * Updated extend.texi. > > This patch adds support for VSX vector arithmetic instructions that may > be added to future PowerPC processors. Note that the names of these > builtins may change in the future. > > New VSX patterns are added for vector add, subtract, multiply, and > multiply-high instructions guarded by TARGET_FUTURE. Existing Altivec > patterns are renamed to altivec_* to avoid name conflicts. > > 2026-05-11 Jeevitha Palanisamy <[email protected]> > > gcc/ > * config/rs6000/altivec.md (*vsx_add<mode>3): New pattern for VSX > vector add for halfword and word. > (*altivec_add<mode>3): Renamed from add<mode>3. > (*vsx_sub<mode>3): New pattern for VSX vector subtract for halfword and > word. > (*altivec_sub<mode>3): Renamed from sub<mode>3. > * config/rs6000/vector.md (VIMulH): New mode iterator for V4SI and V2DI. > (add<mode>3): New expand pattern for integer vector add. > (sub<mode>3): New expand pattern for integer vector subtract. > (smul<mode>3_highpart): New expand pattern for signed vector > multiply-high part on VIMulH modes. > (umul<mode>3_highpart): New expand pattern for unsigned vector > multiply-high part on VIMulH modes. > * config/rs6000/vsx.md (VIArith): New mode iterator for V8HI and V4SI. > (vsx_mul<mode>3): New VSX vector multiply pattern for halfword and word. > (vsx_smul<mode>3_highpart): New VSX signed multiply-high pattern for > halfword and word. > (vsx_umul<mode>3_highpart): New VSX unsigned multiply-high pattern for > halfword and word. > (*altivec_smul<mode>3_highpart): Renamed from smul<mode>3_highpart. > (*altivec_umul<mode>3_highpart): Renamed from umul<mode>3_highpart. > * config/rs6000/rs6000-builtins.def (__builtin_vsx_xvmulhuh): New > builtin for VSX unsigned multiply-high halfword. > (__builtin_vsx_xvmulhsh): New builtin for VSX signed multiply-high > halfword. > * config/rs6000/rs6000-overload.def (__builtin_vec_mulh): Add > overloads for vector multiply-high signed/unsigned halfword. > * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions Available > on Future ISA): Document new functions. > > gcc/testsuite/ > * gcc.target/powerpc/vsx_simd-1.c: New test. > * gcc.target/powerpc/vsx_simd-2.c: New test. > -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
