On Thu, 14 May 2026, Kewen Lin wrote:
> Sorry for getting back to you late, we spent some time discussing with
> hardware team meanwhile making some experiments to confirm back and forth.
>
> > Hygon microarchitecture is derived from first-generation AMD Zen.
>
> AFAIK, floating point and cryptography related supports weren't derived from
> first-generation AMD Zen, so floating point part is different.
Thank you for running the experiments and for the clarification.
> If we consider the best case that FP pipe is only unavailable for first T1
> and last T2,
> do you think we should adjust the modeling to something like:
>
> fpu,divider*N -> (fpu+divider)*T1, divider*(N-T1-T2), (fpu+divider)*T2
>
> Or such modeling can increase the complexity and lead to automaton explosion,
> at the same time the benefits may not be significant on modern machines, we
> can
> just aggressively ignore the difference.
I think precise modeling of pipeline stages (reservation of functional units)
is not important for out-of-order CPUs in GCC. I would recommend to specify
instruction latency accurately ('default_latency' in define_insn_reservation)
as it does not affect automaton size, but for unit reservation pick up some
trade-off between ground truth and reasonably small automaton size.
I don't know how your idea above with 'divider*(N-T1-T2)' will play out; I
suspect it will still blow up the automaton, but maybe reserving the pipe
just for the initial T1+T2 cycles will have less dramatic effect:
fpu,divider*N -> (fpu+divider)*(T1+T2), divider*(N-T1-T2)
In any case, I'd suggest picking a variant with smaller automaton size.
Thank you for working on this.
Alexander
