Gentle ping. Thanks, Lili
> -----Original Message----- > From: Cui, Lili <[email protected]> > Sent: Wednesday, May 13, 2026 9:13 PM > To: Rainer Orth <[email protected]> > Cc: [email protected]; Liu, Hongtao <[email protected]>; > [email protected] > Subject: RE: [PATCH] testsuite: Restrict slp-reduc-15.c to x86_64 and aarch64 > > > > > -----Original Message----- > > From: Rainer Orth <[email protected]> > > Sent: Wednesday, May 13, 2026 4:52 PM > > To: Cui, Lili <[email protected]> > > Cc: [email protected]; Liu, Hongtao <[email protected]>; > > [email protected] > > Subject: Re: [PATCH] testsuite: Restrict slp-reduc-15.c to x86_64 and > > aarch64 > > > > Hi Lili, > > > > > diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > > > b/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > > > index 4745f85511b..d22114d6960 100644 > > > --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > > > +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > > > @@ -1,6 +1,7 @@ > > > -/* { dg-do compile } */ > > > -/* { dg-require-effective-target vect_float } */ > > > -/* { dg-additional-options "-fgimple -march=x86-64-v3" { target > > > x86_64-*-* } } */ > > > +/* { dg-do compile { target { x86_64-*-* || aarch64-*-* } } } */ > > > +/* { dg-additional-options "-fgimple" } */ > > > +/* { dg-additional-options "-march=x86-64-v3" { target x86_64-*-* } > > > +} */ > > > > using unadorned target x86_64-*-* is always wrong: a multilibbed > > i386-*-* target with -m64 also generates 64-bit code. If you want to > > restrict the test to 64-bit x86, use target { x86 && lp64 } instead. > > > Hi Rainer, > > Thank you for the feedback and the clear explanation about the target selector > issue. > I've updated the test to use { x86 && lp64 } instead of x86_64-*-*, which > properly handles both i386-*-* configurations with -m64 and excludes > x86_64-*-* with -m32. > > diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > b/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > index 4745f85511b..e8cce237c20 100644 > --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c > @@ -1,6 +1,7 @@ > -/* { dg-do compile } */ > -/* { dg-require-effective-target vect_float } */ > -/* { dg-additional-options "-fgimple -march=x86-64-v3" { target x86_64-*- > * } } */ > +/* { dg-do compile { target { { x86 && lp64 } || aarch64-*-* } } } */ > +/* { dg-additional-options "-fgimple" } */ > +/* { dg-additional-options "-march=x86-64-v3" { target { x86 && lp64 } > +} } */ > +/* { dg-additional-options "-march=armv8.2-a+sve" { target aarch64-*-* > +} } */ > > /* Test that SLP reduction vectorization handles commutative operand swap > for .COND_ADD in multi-lane SLP where the reduction operand appears @@ > -76,6 +77,6 @@ foo (float * restrict p0, float * restrict p1, > > /* With the IFN commutative swap fix, these 4 reductions should be > vectorized using SLP despite different reduc_idx values (1 vs 2). */ > -/* { dg-final { scan-tree-dump "swapped operands to match def types in" > "vect" { target x86_64-*-* } } } */ > -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" > { target x86_64-*-* } } } */ > +/* { dg-final { scan-tree-dump "swapped operands to match def types in" > +"vect" } } */ > +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 > +"vect" } } */ > > Tested on aarch64 and x86_64. OK for trunk? > > Thanks, > Lili. > > > Rainer > > > > -- > > ---------------------------------------------------------------------- > > ------- Rainer Orth, Center for Biotechnology, Bielefeld University
