[PATCH] riscv: Fix SSP assembly with xtheadmemidx [PR 125320]

[Xi Ruoyao]

The m constriant accepts memory operands suitable for memory load/store
instructions in extensions, not only the ld/sd instructions.  So we
cannot always use ld/sd in the SSP instruction sequences.

Call riscv_output_move() for the correct assembly template instead.

        PR target/125320

gcc/

        * config/riscv/riscv.md (stack_protect_test_<mode>): Call
        riscv_output_move() instead of hard coding <load>.
        (stack_protect_set_<mode>): Call riscv_output_move() instead of
        hard coding <load> and <store>.

gcc/testsuite/

        * gcc.target/riscv/pr125320.c: New test.
---

Ok for trunk and 16.2?

 gcc/config/riscv/riscv.md                 | 16 ++++++++++++++--
 gcc/testsuite/gcc.target/riscv/pr125320.c | 10 ++++++++++
 2 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr125320.c

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 869061e18ae..83056e27ce5 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4481,7 +4481,13 @@ (define_insn "stack_protect_set_<mode>"
         UNSPEC_SSP_SET))
    (set (match_scratch:GPR 2 "=&r") (const_int 0))]
   ""
-  "<load>\t%2, %1\;<store>\t%2, %0\;li\t%2, 0"
+  {
+    for (auto op: (rtx[][2]){{operands[2], operands[1]},
+                            {operands[0], operands[2]}})
+      output_asm_insn (riscv_output_move (op[0], op[1]), op);
+
+    return "li\t%2, 0";
+  }
   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 
@@ -4521,7 +4527,13 @@ (define_insn "stack_protect_test_<mode>"
         UNSPEC_SSP_TEST))
    (clobber (match_scratch:GPR 3 "=&r"))]
   ""
-  "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
+  {
+    for (auto op: (rtx[][2]){{operands[3], operands[1]},
+                            {operands[0], operands[2]}})
+      output_asm_insn (riscv_output_move (op[0], op[1]), op);
+
+    return "xor\t%0, %3, %0\;li\t%3, 0";
+  }
   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr125320.c 
b/gcc/testsuite/gcc.target/riscv/pr125320.c
new file mode 100644
index 00000000000..2bc33ce0dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr125320.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mabi=lp64d -march=rv64gc_xtheadmemidx 
-fstack-protector-strong" } */
+
+void __gen_tempname (char *, int, int, int);
+void
+tempnam ()
+{
+  char buf[4096];
+  __gen_tempname (buf, 0, 0, 2);
+}
-- 
2.54.0