> -----Original Message-----
> From: Richard Biener <[email protected]>
> Sent: Friday, May 15, 2026 4:21 PM
> To: Cui, Lili <[email protected]>
> Cc: [email protected]; Liu, Hongtao <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH V3] testsuite: Add aarch64 SVE support to slp-reduc-15.c
>
> On Fri, 15 May 2026, Lili Cui wrote:
>
> > Thanks to H.J for the suggestions on v2. I realized the original x86-64-v3
> option was awkward to handle with different x86 modes, so v3 switches to -
> mavx2 which works cleanly with -m32, -m64, and -mx32.
> >
> > Changes in v3:
> > - Add aarch64 SVE support with -march=armv8.2-a+sve
> > - Use -mavx2 instead of -march=x86-64-v3 to support all x86
> > modes(-m32, -m64, -mx32)
> >
> > Tested on aarch64 and x86_64. OK for trunk?
>
> OK.
Committed, thanks！
Lili.
>
> > Thanks,
> > Lili.
> >
> >
> >
> > Add aarch64 SVE support and use -mavx2 for x86 to support all x86
> > modes.
> >
> > Changes:
> > - Add aarch64-*-* target with -march=armv8.2-a+sve
> > - Use -mavx2 instead of -march=x86-64-v3 to support all x86 modes
> > - Separate -fgimple from architecture-specific options.
> >
> > Reported-by: https://linaro.atlassian.net/browse/GNU-1901
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.dg/vect/slp-reduc-15.c: Add aarch64 support and use
> > -mavx2 for x86.
> > ---
> > gcc/testsuite/gcc.dg/vect/slp-reduc-15.c | 11 ++++++-----
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c
> > b/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c
> > index 4745f85511b..a28c13a92f5 100644
> > --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c
> > +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-15.c
> > @@ -1,6 +1,7 @@
> > -/* { dg-do compile } */
> > -/* { dg-require-effective-target vect_float } */
> > -/* { dg-additional-options "-fgimple -march=x86-64-v3" { target
> > x86_64-*-* } } */
> > +/* { dg-do compile { target { x86 || aarch64-*-* } } } */
> > +/* { dg-additional-options "-fgimple" } */
> > +/* { dg-additional-options "-mavx2" { target x86 } } */
> > +/* { dg-additional-options "-march=armv8.2-a+sve" { target
> > +aarch64-*-* } } */
> >
> > /* Test that SLP reduction vectorization handles commutative operand swap
> > for .COND_ADD in multi-lane SLP where the reduction operand
> > appears @@ -76,6 +77,6 @@ foo (float * restrict p0, float * restrict
> > p1,
> >
> > /* With the IFN commutative swap fix, these 4 reductions should be
> > vectorized using SLP despite different reduc_idx values (1 vs 2).
> > */
> > -/* { dg-final { scan-tree-dump "swapped operands to match def types
> > in" "vect" { target x86_64-*-* } } } */
> > -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4
> > "vect" { target x86_64-*-* } } } */
> > +/* { dg-final { scan-tree-dump "swapped operands to match def types
> > +in" "vect" } } */
> > +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4
> > +"vect" } } */
> >
> >
>
> --
> Richard Biener <[email protected]>
> SUSE Software Solutions Germany GmbH,
> Frankenstrasse 146, 90461 Nuernberg, Germany;
> GF: Jochen Jaser, Andrew McDonald, Werner Knoblich; (HRB 36809, AG
> Nuernberg)
