Hi Christoph:
Thanks for the patch! here is only few review comments below :)
> +bool
> +riscv_zilsd_valid_mem_p (rtx mem, machine_mode mode)
> +{
> + return (TARGET_ZILSD
> + && !TARGET_64BIT
Let drop `!TARGET_64BIT`, that should already guarded when parsing march
> + && riscv_2x_xlen_mode_p (mode)
> + && MEM_P (mem)
> + && MEM_ALIGN (mem) >= riscv_zilsd_required_align () *
> BITS_PER_UNIT);
> +}
> +
> +/* Return the effective Zilsd memory access alignment policy. */
> +
> +static unsigned int
> +riscv_zilsd_required_align (const struct cl_target_option *opts)
> +{
> + return riscv_zilsd_required_align
> + (opts->x_riscv_zilsd_align, TARGET_STRICT_ALIGN_P
> (opts->x_target_flags));
> +}
> +
> /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
>
> static unsigned int
> @@ -5014,6 +5073,53 @@ riscv_split_64bit_move_p (rtx dest, rtx src)
> return true;
> }
>
> +/* Expand a potentially misaligned Zilsd-sized memory move. */
> +
> +void
> +riscv_expand_zilsd_misaligned_move (rtx dest, rtx src)
I incline this return a bool value and let it FAIL to expand by
default expand logic instead we repeats those logic here unless we
have better expand logic.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 869061e18ae..7be0181c163 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2578,6 +2578,15 @@ (define_insn "*movdi_64bit"
> (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fmove,fpstore,move")
> (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
>
> +(define_expand "movmisaligndi"
> + [(set (match_operand:DI 0 "nonimmediate_operand")
> + (match_operand:DI 1 "general_operand"))]
> + "!TARGET_64BIT && TARGET_ZILSD"
> +{
> + riscv_expand_zilsd_misaligned_move (operands[0], operands[1]);
e.g.
if (riscv_expand_zilsd_misaligned_move (operands[0], operands[1]))
DONE;
else
FAIL;
> @@ -2752,6 +2761,15 @@ (define_insn "*movdf_softfloat"
> (set_attr "type" "fmove,fpload,fpstore")
> (set_attr "mode" "DF")])
>
> +(define_expand "movmisaligndf"
> + [(set (match_operand:DF 0 "nonimmediate_operand")
> + (match_operand:DF 1 "general_operand"))]
> + "!TARGET_64BIT && TARGET_ZILSD && !TARGET_DOUBLE_FLOAT"
I guess we probably could still expand with TARGET_DOUBLE_FLOAT here,
because without this pattern we might got 8 load byte and then combine
then move to FPR
(either via memory or just GPR<->FPR).
https://godbolt.org/z/hG3411jMY
