Am 19.05.26 um 09:32 schrieb Denis Chertykov:
пн, 18 мая 2026 г. в 12:14, Georg-Johann Lay <[email protected]>:
This patch adds insns for 16-bit and 32-bit __builtin_bitreverse.
With the patch, the generated code has a better size / speed ratio.
The patch uses hard-reg constraints, which is possible since the
code generation doesn't rely on insn combine.
Passes without new regressions. Ok for trunk?
Ok.
Please apply.
Denis
Meanwhile, a patch has been applied that expresses bitreverse in
terms of wider / shorter bitreverse when there is no insn for the
former. So the assumption is basically
insn available <=> insn is cheap
https://gcc.gnu.org/r17-591
For the avr BE this means that the 8-bit bitreverse is now
expressed in terms of the 16-bit one. Therefore, I also
added bitreverseqi2 insns.
https://gcc.gnu.org/r17-598
Johann
--
AVR: Add bitreverseqi2 insns.
Now that https://gcc.gnu.org/r17-591 has been applied, the
middle-end will express 8-bit bitreverse code in terms of
a 16-bit bitreverse. Therefore, add bitreverseqi2 insns.
gcc/
* config/avr/avr.md (bitreverseqi2): New insn-and-split.
(*bitreverseqi2): New insn.
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -9039,6 +9039,43 @@ (define_insn_and_split "*popcountqihi2.libgcc"
;; Bit Reverse
+(define_insn_and_split "bitreverseqi2"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (bitreverse:QI (match_operand:QI 1 "register_operand" "r")))]
+ ""
+ "#"
+ "&& reload_completed"
+ [(scratch)]
+ { DONE_ADD_CCC })
+
+(define_insn "*bitreverseqi2"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (bitreverse:QI (match_operand:QI 1 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
+ {
+ return REGNO (operands[0]) == REGNO (operands[1])
+ ? "mov __tmp_reg__,%0" CR_TAB
+ "lsl %0" CR_TAB
+ "adc %0,__zero_reg__" CR_TAB
+ "bst __tmp_reg__,0 $ bld %0,7" CR_TAB
+ "bst __tmp_reg__,1 $ bld %0,6" CR_TAB
+ "bst __tmp_reg__,2 $ bld %0,5" CR_TAB
+ "bst __tmp_reg__,4 $ bld %0,3" CR_TAB
+ "bst __tmp_reg__,5 $ bld %0,2" CR_TAB
+ "bst __tmp_reg__,6 $ bld %0,1"
+ : "mov %0,%1" CR_TAB
+ "lsl %0" CR_TAB
+ "adc %0,__zero_reg__" CR_TAB
+ "bst %1,0 $ bld %0,7" CR_TAB
+ "bst %1,1 $ bld %0,6" CR_TAB
+ "bst %1,2 $ bld %0,5" CR_TAB
+ "bst %1,4 $ bld %0,3" CR_TAB
+ "bst %1,5 $ bld %0,2" CR_TAB
+ "bst %1,6 $ bld %0,1";
+ }
+ [(set_attr "length" "15")])
+
(define_insn_and_split "bitreversehi2"
[(set (match_operand:HI 0 "register_operand" "={r24}")
(bitreverse:HI (match_operand:HI 1 "register_operand" "{r24}")))]
