On Wed, May 13, 2026 at 03:17:39AM -0500, Manjunath S Matti wrote:
> The changes have been bootstrapped and regression tested on
> powerpc64le-linux.
>
> Changes from V1:
> * Commit message formatted to 72 character lenght.
> * Changed to 'Future ISA' instead of 'ISA 3.2'.
> * Listed down all the new UNSPEC, instruction patterns and builtin names
> in the Changelog entries.
> * Removed the type and size attribute for all the 21 new instruction
> patterns.
> * Removed detailed description for the builtins in extend.texi.
>
> This patch implements builtin support for 21 new ECC (Elliptic Curve
> Cryptography) acceleration instructions defined in RFC02669 for Power
> future ISA. These instructions are designed to accelerate P-256 and
> P-384 elliptic curve operations on POWER future processors. These
> instructions may or may not be supported in a future processor. Note,
> the names of the builtins may change in future.
>
> The instructions are organized into five categories:
>
> 1. Multiply-Multiply operations (3 instructions):
> - xxmulmul: Multiply-multiply with scaling (scale values 0-6)
> - xxmulmulhiadd: Multiply-multiply with high add and accumulator
> - xxmulmulloadd: Multiply-multiply low add with accumulator
>
> 2. Scaled Multiply-Sum operations (3 instructions):
> - xxssumudm: Scaled sum unsigned doubleword modulo
> - xxssumudmc: Scaled sum unsigned doubleword modulo carry
> - xxssumudmcext: Extended version with separate accumulator
> (prefixed)
>
> 3. Quadword Add/Subtract operations (4 instructions):
> - xsaddadduqm: Add add unsigned quadword modulo
> - xsaddaddsuqm: Add add scaled unsigned quadword modulo
> - xsaddsubuqm: Add subtract unsigned quadword modulo
> - xsaddsubsuqm: Add subtract scaled unsigned quadword modulo
>
> 4. Merge operations (4 instructions):
> - xsmerge2t1uqm, xsmerge2t2uqm, xsmerge2t3uqm: 2-operand merge
> - xsmerge3t1uqm: 3-operand merge with accumulator
>
> 5. Rebase operations (7 instructions):
> - xsrebase2t1uqm through xsrebase2t4uqm: 2-operand rebase
> - xsrebase3t1uqm through xsrebase3t3uqm: 3-operand rebase with
> accumulator
>
> All instructions operate on 128-bit unsigned integers
> (vector unsigned __int128) and use VSX registers.
> The xxssumudmcext instruction is a prefixed instruction (8 bytes),
> while all others use the standard XX3 form (4 bytes).
Generally these are fine. I assume you have run the tests through the
binutils assembler that supports these instructions just to make there
is not a mismatch between the compiler and assembler.
However, all of the tests need guards on then to make sure the compiler
supports -mcpu=future and is generating 64-bit code (__int128 is not
supported on 32-bit bit endian systems).
I.e.
/* { dg-require-effective-target powerpc_future_ok } */
/* { dg-require-effective-target lp64 } */
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
