On Thu, May 14, 2026 at 9:26 PM Uros Bizjak <[email protected]> wrote:
>
> All supported versions of GNU as automatically encode "sal $1, reg"
> using the shorter implicit-count-1 form (opcode D1), making the
> compiler-side i486 TARGET_SHIFT1 / X86_TUNE_SHIFT1 logic redundant.
>
> Remove the tuning feature and simplify all affected shift instruction
> patterns by unconditionally emitting the explicit-immediate form and
> relying on the assembler to produce the optimal encoding.  Update the
> length_immediate attributes accordingly to report 0 for const-1 shift
> counts, correctly reflecting the assembled output.
>
> gcc/ChangeLog:
>
>     * config/i386/x86-tune.def (X86_TUNE_SHIFT1): Remove.
>     * config/i386/i386.h (TARGET_SHIFT1): Remove.
>     * config/i386/i386.md (*ashl<mode>3_1<nf_name>): Remove
>     TARGET_SHIFT1-gated implicit-1 encoding and simplify
>     length_immediate attribute.
>     (*ashlsi3_1_zext): Likewise.
>     (*ashlhi3_1<nf_name>): Likewise.
>     (*ashlqi3_1<nf_name>): Likewise.
>     (*ashl<mode>3_1_slp): Likewise.
>     (*ashl<mode>3_cmp): Likewise.
>     (*ashlsi3_cmp): Likewise.
>     (*<any_shiftrt:insn><mode>3_1<nf_name>): Likewise.
>     (*<any_shiftrt:insn>si3_1_zext): Likewise.
>     (*<any_shiftrt:insn><mode>3_1_slp): Likewise.
>     (*<any_shiftrt:insn><mode>3_cconly): Likewise.
>     (*<any_shiftrt:insn>qi_ext<mode>_1): Likewise.
>     (<any_shiftrt:insn><mode>3_carry): Likewise.
>
> Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.

Now committed to mainline.

Uros.

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