Hello, Below patch is bootstrapped and regtested on powerpc64le-linux-gnu with no regressions.
Thank You, Kishan The rs6000 built-in infrastructure previously supported only a single gating predicate per built-in stanza. This caused issues when a built-in required multiple conditions to be satisfied. For example, __builtin_vsx_xvtlsbb_all_ones requires both Power10 ISA support (-mcpu=power10) and VSX support (-mvsx), but was only gated on [power10], causing compiler crashes when compiled with -mcpu=power10 -mno-vsx. This patch extends the built-in infrastructure to support up to 4 comma-separated gating predicates in stanza headers (e.g., [power10, vsx]). All predicates are combined with AND logic - all must be satisfied for the built-in to be enabled. Note: I've just put one builtin for now under [power10, vsx]. The rs6000-builtins.def file requires rework. This also maintains full backward compatibility with existing single-predicate stanzas. 2026-05-21 Kishan Parmar <[email protected]> gcc/ChangeLog: * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Check all predicates and report all missing requirements in single error message. (get_enable_string): New helper function to map enable enums to option strings. (rs6000_builtin_is_supported): Implement AND logic for multiple predicates. (check_single_enable): New helper function. * config/rs6000/rs6000-builtins.def: Update documentation to explain comma-separated predicate syntax. Move __builtin_vsx_xvtlsbb_all_ones under power10 AND vsx. * config/rs6000/rs6000-gen-builtins.cc (MAXBIFPREDICATES): New constant. (struct bifdata): Add num_predicates and predicates fields. (parse_bif_stanza_predicates): New function to parse comma-separated gating predicates in stanza header. (parse_bif_entry): Fill predicates and num_predicates fields of bifs. (parse_bif_stanza): Call to parse_bif_stanza_predicates. (write_decls): Generate header from bifdata structure by replacing the single bif_enable field with a bif_enable array and extra num_enables field. (write_bif_static_init): Fill num_enables and bif_enable enables fields for every bifs. gcc/testsuite/ChangeLog: * gcc.target/powerpc/cmpb-2.c: Fix expected option diagnostics. * gcc.target/powerpc/pragma_misc9.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/p10-vsx-bif.c: New test. --- gcc/config/rs6000/rs6000-builtin.cc | 152 +++++++++++------- gcc/config/rs6000/rs6000-builtins.def | 25 ++- gcc/config/rs6000/rs6000-gen-builtins.cc | 107 +++++++++++- gcc/testsuite/gcc.target/powerpc/cmpb-2.c | 2 +- .../gcc.target/powerpc/p10-vsx-bif.c | 11 ++ .../gcc.target/powerpc/pragma_misc9.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-7.c | 2 +- .../gcc.target/powerpc/vsu/vec-any-eqz-7.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpnez-7.c | 2 +- .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c | 2 +- .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c | 2 +- 11 files changed, 227 insertions(+), 84 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/p10-vsx-bif.c diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 4d0e541351f..323b2e7c38d 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -62,98 +62,68 @@ tree altivec_builtin_mask_for_load; /* **** General support functions **** */ -/* Raise an error message for a builtin function that is called without the - appropriate target options being set. */ +/* Helper function to get the option string for a single enable predicate. */ -void -rs6000_invalid_builtin (enum rs6000_gen_builtins fncode) +static const char * +get_enable_string (bif_enable enable) { - size_t j = (size_t) fncode; - const char *name = rs6000_builtin_info[j].bifname; - - switch (rs6000_builtin_info[j].enable) + switch (enable) { case ENB_P5: - error ("%qs requires the %qs option", name, "-mcpu=power5"); - break; + return "-mcpu=power5"; case ENB_P6: - error ("%qs requires the %qs option", name, "-mcpu=power6"); - break; + return "-mcpu=power6"; case ENB_P6_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power6", "-m64", "-mpowerpc64"); - break; + return "-mcpu=power6 and either -m64 or -mpowerpc64"; case ENB_ALTIVEC: - error ("%qs requires the %qs option", name, "-maltivec"); - break; + return "-maltivec"; case ENB_CELL: - error ("%qs requires the %qs option", name, "-mcpu=cell"); - break; + return "-mcpu=cell"; case ENB_VSX: - error ("%qs requires the %qs option", name, "-mvsx"); - break; + return "-mvsx"; case ENB_P7: - error ("%qs requires the %qs option", name, "-mcpu=power7"); - break; + return "-mcpu=power7"; case ENB_P7_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power7", "-m64", "-mpowerpc64"); - break; + return "-mcpu=power7 and either -m64 or -mpowerpc64"; case ENB_P8: - error ("%qs requires the %qs option", name, "-mcpu=power8"); - break; + return "-mcpu=power8"; case ENB_P8V: - error ("%qs requires the %qs and %qs options", name, "-mcpu=power8", - "-mvsx"); - break; + return "-mcpu=power8 and -mvsx"; case ENB_P9: - error ("%qs requires the %qs option", name, "-mcpu=power9"); - break; + return "-mcpu=power9"; case ENB_P9_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power9", "-m64", "-mpowerpc64"); - break; + return "-mcpu=power9 and either -m64 or -mpowerpc64"; case ENB_P9V: - error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", - "-mvsx"); - break; + return "-mcpu=power9 and -mvsx"; case ENB_IEEE128_HW: - error ("%qs requires quad-precision floating-point arithmetic", name); - break; + return "quad-precision floating-point arithmetic"; case ENB_DFP: - error ("%qs requires the %qs option", name, "-mhard-dfp"); - break; + return "-mhard-dfp"; case ENB_CRYPTO: - error ("%qs requires the %qs option", name, "-mcrypto"); - break; + return "-mcrypto"; case ENB_HTM: - error ("%qs requires the %qs option", name, "-mhtm"); - break; + return "-mhtm"; case ENB_P10: - error ("%qs requires the %qs option", name, "-mcpu=power10"); - break; + return "-mcpu=power10"; case ENB_P10_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power10", "-m64", "-mpowerpc64"); - break; + return "-mcpu=power10 and either -m64 or -mpowerpc64"; case ENB_MMA: - error ("%qs requires the %qs option", name, "-mmma"); - break; + return "-mmma"; case ENB_FUTURE: - error ("%qs requires the %qs option", name, "-mcpu=future"); - break; + return "-mcpu=future"; default: case ENB_ALWAYS: gcc_unreachable (); } + gcc_unreachable (); } -/* Check whether a builtin function is supported in this target - configuration. */ -bool -rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) +/* Helper function to check if a single enable predicate is satisfied. */ + +static bool +check_single_enable (bif_enable enable) { - switch (rs6000_builtin_info[(size_t) fncode].enable) + switch (enable) { case ENB_ALWAYS: return true; @@ -205,6 +175,66 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) gcc_unreachable (); } +/* Raise an error message for a builtin function that is called without the + appropriate target options being set. For functions with multiple gating + predicates, report all missing requirements. */ + +void +rs6000_invalid_builtin (enum rs6000_gen_builtins fncode) +{ + size_t j = (size_t) fncode; + const char *name = rs6000_builtin_info[j].bifname; + int num_enables = rs6000_builtin_info[j].num_enables; + + /* Collect all missing requirements. */ + const char *missing[PPC_MAXBIFPREDICATES]; + int num_missing = 0; + + for (int i = 0; i < num_enables; i++) + { + if (!check_single_enable (rs6000_builtin_info[j].enables[i])) + missing[num_missing++] = get_enable_string (rs6000_builtin_info[j].enables[i]); + } + + /* Report the error with all missing requirements. */ + if (num_missing == 1) + { + if (strstr (missing[0], " and ")) + error ("%qs requires the %qs options", name, missing[0]); + else + error ("%qs requires the %qs option", name, missing[0]); + } + else if (num_missing == 2) + error ("%qs requires the %qs and %qs options", + name, missing[0], missing[1]); + else if (num_missing == 3) + error ("%qs requires the %qs, %qs, and %qs options", + name, missing[0], missing[1], missing[2]); + else if (num_missing == 4) + error ("%qs requires the %qs, %qs, %qs, and %qs options", + name, missing[0], missing[1], missing[2], missing[3]); +} + +/* Check whether a builtin function is supported in this target + configuration. For functions with multiple gating predicates, + ALL predicates must be satisfied (AND logic). */ + +bool +rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) +{ + size_t j = (size_t) fncode; + int num_enables = rs6000_builtin_info[j].num_enables; + + /* Check all enable predicates - ALL must be true (AND logic). */ + for (int i = 0; i < num_enables; i++) + { + if (!check_single_enable (rs6000_builtin_info[j].enables[i])) + return false; + } + + return true; +} + /* Target hook for early folding of built-ins, shamelessly stolen from ia64.cc. */ diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 0d1529b71d4..07d24069772 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -31,7 +31,15 @@ ; ; [power9] ; -; The bracketed gating predicate is the only information allowed on +; Multiple gating predicates can be specified using comma-separated values. +; When multiple predicates are specified, ALL predicates must be satisfied +; (AND logic) for the built-in to be enabled. For example: +; +; [power10,vsx] +; +; This means the built-in requires both -mcpu=power10 AND -mvsx options. +; +; The bracketed gating predicate(s) are the only information allowed on ; the stanza header line, other than whitespace. ; ; Following the stanza header are two lines for each function: the @@ -3318,12 +3326,6 @@ const vuq __builtin_vsx_vmsumcud (vull, vull, vuq); VMSUMCUD vmsumcud {} - const signed int __builtin_vsx_xvtlsbb_all_ones (vsc); - XVTLSBB_ONES xvtlsbbo {} - - const signed int __builtin_vsx_xvtlsbb_all_zeros (vsc); - XVTLSBB_ZEROS xvtlsbbz {} - const vf __builtin_vsx_vxxsplti32dx_v4sf (vf, const int<1>, float); VXXSPLTI32DX_V4SF xxsplti32dx_v4sf {} @@ -3425,6 +3427,15 @@ ZE_LXVRDX vsx_lxvrdx {lxvrze} +; Power10 VSX builtins that requires -mvsx. +[power10, vsx] + const signed int __builtin_vsx_xvtlsbb_all_ones (vsc); + XVTLSBB_ONES xvtlsbbo {} + + const signed int __builtin_vsx_xvtlsbb_all_zeros (vsc); + XVTLSBB_ZEROS xvtlsbbz {} + + [power10-64] const unsigned long long __builtin_cfuged (unsigned long long, \ unsigned long long); diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc b/gcc/config/rs6000/rs6000-gen-builtins.cc index 7436404cff5..ef4d039a620 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.cc +++ b/gcc/config/rs6000/rs6000-gen-builtins.cc @@ -39,7 +39,15 @@ along with GCC; see the file COPYING3. If not see [power9] - The bracketed gating predicate is the only information allowed on + Multiple gating predicates can be specified using comma-separated + values. When multiple predicates are specified, ALL predicates must + be satisfied (AND logic) for the built-in to be enabled. For example: + + [power10,vsx] + + This means the built-in requires both -mcpu=power10 AND -mvsx options. + + The bracketed gating predicate(s) are the only information allowed on the stanza header line, other than whitespace. Following the stanza header are two lines for each function: the @@ -236,7 +244,13 @@ enum bif_stanza NUMBIFSTANZAS }; +/* Maximum number of predicates that can be specified for a single + stanza. */ +#define MAXBIFPREDICATES 4 + static bif_stanza curr_bif_stanza; +static int curr_bif_num_predicates = 0; +static bif_stanza curr_bif_predicates[MAXBIFPREDICATES]; struct stanza_entry { @@ -416,6 +430,8 @@ struct prototype struct bifdata { int stanza; + int num_predicates; + int predicates[MAXBIFPREDICATES]; fnkinds kind; prototype proto; char *idname; @@ -819,6 +835,57 @@ stanza_name_to_stanza (const char *stanza_name) return BSTZ_ALWAYS; } +/* Parse comma-separated gating predicates from a stanza header and populate + the predicates array. Each predicate is specified by a stanza name (e.g., + "power10", "vsx") that represents a gating condition that must be satisfied + for the built-in to be enabled. Multiple predicates are combined with AND + logic. Returns the number of predicates parsed. The input string is + modified (commas replaced with null terminators). */ + +static int +parse_bif_stanza_predicates (char *predicates_str, bif_stanza *predicates) +{ + int num_predicates = 0; + char *predicate_name = predicates_str; + char *comma_pos; + + while (predicate_name && num_predicates < MAXBIFPREDICATES) + { + /* Find the next comma or end of string. */ + comma_pos = strchr (predicate_name, ','); + if (comma_pos) + *comma_pos = '\0'; + + /* Trim leading and trailing whitespace from predicate name. */ + while (*predicate_name == ' ' || *predicate_name == '\t') + predicate_name++; + + char *end = predicate_name + strlen (predicate_name) - 1; + while (end > predicate_name && (*end == ' ' || *end == '\t')) + { + *end = '\0'; + end--; + } + + if (*predicate_name != '\0') + { + /* Convert predicate name (stanza name) to stanza enum. */ + predicates[num_predicates] = stanza_name_to_stanza (predicate_name); + num_predicates++; + } + + if (comma_pos) + predicate_name = comma_pos + 1; + else + break; + } + + if (num_predicates >= MAXBIFPREDICATES && strchr (predicate_name, ',')) + fatal ("Too many predicates in stanza header.\n"); + + return num_predicates; +} + /* Match one of the allowable base types. Consumes one token unless the token is "long", which must be paired with a second "long". Optionally consumes a following '*' token for pointers. Return 1 for success, @@ -1794,6 +1861,9 @@ parse_bif_entry (void) curr_bif = num_bifs++; bifs[curr_bif].stanza = curr_bif_stanza; + bifs[curr_bif].num_predicates = curr_bif_num_predicates; + for (int i = 0; i < curr_bif_num_predicates; i++) + bifs[curr_bif].predicates[i] = curr_bif_predicates[i]; /* Read the first token and see if it is a function modifier. */ consume_whitespace (); @@ -1899,14 +1969,24 @@ parse_bif_stanza (void) } safe_inc_pos (); - const char *stanza_name = match_to_right_bracket (); - if (!stanza_name) + const char *stanza_name_const = match_to_right_bracket (); + if (!stanza_name_const) { diag (pos, "no expression found in stanza header.\n"); return PC_PARSEFAIL; } - curr_bif_stanza = stanza_name_to_stanza (stanza_name); + /* Make a mutable copy since parse_bif_stanza_predicates modifies the string. */ + char *stanza_name = strdup (stanza_name_const); + + /* Parse comma-separated gating predicates from the stanza header. */ + curr_bif_num_predicates = parse_bif_stanza_predicates (stanza_name, curr_bif_predicates); + + /* Free the duplicated string. */ + free (stanza_name); + + /* Store the primary (first) stanza in curr_bif_stanza for backward compatibility. */ + curr_bif_stanza = curr_bif_predicates[0]; if (linebuf[pos] != ']') { @@ -2257,10 +2337,12 @@ write_decls (void) fprintf (header_file, "};\n\n"); fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n"); + fprintf (header_file, "#define PPC_MAXBIFPREDICATES 4\n"); fprintf (header_file, "struct bifdata\n"); fprintf (header_file, "{\n"); fprintf (header_file, " const char *bifname;\n"); - fprintf (header_file, " bif_enable enable;\n"); + fprintf (header_file, " int num_enables;\n"); + fprintf (header_file, " bif_enable enables[PPC_MAXBIFPREDICATES];\n"); fprintf (header_file, " insn_code icode;\n"); fprintf (header_file, " int nargs;\n"); fprintf (header_file, " int bifattrs;\n"); @@ -2478,7 +2560,7 @@ write_bif_static_init (void) fprintf (init_file, "bifdata rs6000_builtin_info[RS6000_BIF_MAX] =\n"); fprintf (init_file, " {\n"); fprintf (init_file, " { /* RS6000_BIF_NONE: */\n"); - fprintf (init_file, " \"\", ENB_ALWAYS, CODE_FOR_nothing, 0,\n"); + fprintf (init_file, " \"\", 0, {ENB_ALWAYS}, CODE_FOR_nothing, 0,\n"); fprintf (init_file, " 0, {0, 0, 0}, {RES_NONE, RES_NONE, RES_NONE},\n"); fprintf (init_file, " {0, 0, 0}, {0, 0, 0}, \"\", RS6000_BIF_NONE\n"); fprintf (init_file, " },\n"); @@ -2488,8 +2570,17 @@ write_bif_static_init (void) fprintf (init_file, " { /* RS6000_BIF_%s: */\n", bifp->idname); fprintf (init_file, " /* bifname */\t\"%s\",\n", bifp->proto.bifname); - fprintf (init_file, " /* enable*/\t%s,\n", - enable_string[bifp->stanza]); + /* Output num_enables and enables array. */ + fprintf (init_file, " /* num_enables */\t%d,\n", + bifp->num_predicates); + fprintf (init_file, " /* enables */\t{"); + for (int j = 0; j < bifp->num_predicates; j++) + { + if (j > 0) + fprintf (init_file, ", "); + fprintf (init_file, "%s", enable_string[bifp->predicates[j]]); + } + fprintf (init_file, "},\n"); fprintf (init_file, " /* icode */\tCODE_FOR_%s,\n", bifp->patname); fprintf (init_file, " /* nargs */\t%d,\n", diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c index 44a554bee4a..3da27e37d9b 100644 --- a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c @@ -9,7 +9,7 @@ void abort (); unsigned long long int do_compare (unsigned long long int a, unsigned long long int b) { - return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6' option" } */ + return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6 and either -m64 or -mpowerpc64' options" } */ } void diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vsx-bif.c b/gcc/testsuite/gcc.target/powerpc/p10-vsx-bif.c new file mode 100644 index 00000000000..2bc90530028 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p10-vsx-bif.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-mdejagnu-cpu=power10 -mno-vsx" } */ + +extern __vector signed char a; + +int main() +{ + return __builtin_vsx_xvtlsbb_all_ones (a); + /* { dg-error "'__builtin_vsx_xvtlsbb_all_ones' requires the '-mvsx' option" "" { target *-*-* } .-1 } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c index 03e4bf0b31a..ca58d0eea0f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c +++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c @@ -20,7 +20,7 @@ vector bool int test2 (vector signed int a, vector signed int b) { return vec_cmpnez (a, b); - /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' and '-mvsx' options" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9 and -mvsx' options" "" { target *-*-* } .-1 } */ } #pragma GCC target ("cpu=power7") @@ -28,7 +28,7 @@ vector signed int test3 (vector signed int a, vector signed int b) { return vec_mergee (a, b); - /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mcpu=power8' and '-mvsx' options" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mcpu=power8 and -mvsx' options" "" { target *-*-* } .-1 } */ } #pragma GCC target ("cpu=power6") diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c index bf44953e978..53ec63e1b71 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c @@ -12,5 +12,5 @@ test_all_not_equal_and_not_zero (vector unsigned short *arg1_p, vector unsigned short arg_2 = *arg2_p; return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2); - /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9' and '-mvsx' options" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9 and -mvsx' options" "" { target *-*-* } .-1 } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c index 3af1b3104d1..584829420aa 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c @@ -11,5 +11,5 @@ test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p) vector unsigned int arg_2 = *arg2_p; return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2); - /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9' and '-mvsx' options" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9 and -mvsx' options" "" { target *-*-* } .-1 } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c index 7174eba1b22..8d399de1a1d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c @@ -10,5 +10,5 @@ fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p) vector unsigned int arg_1 = *arg1_p; vector unsigned int arg_2 = *arg2_p; - return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' and '-mvsx' options" } */ + return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9 and -mvsx' options" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c index b952efc1be1..723ac97ec28 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c @@ -9,5 +9,5 @@ count_leading_zero_byte_bits (vector unsigned char *arg1_p) { vector unsigned char arg_1 = *arg1_p; - return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mcpu=power9' and '-mvsx' options" } */ + return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mcpu=power9 and -mvsx' options" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c index c8ecb051809..7c9d68ee4dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c @@ -9,5 +9,5 @@ count_trailing_zero_byte_bits (vector unsigned char *arg1_p) { vector unsigned char arg_1 = *arg1_p; - return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mcpu=power9' and '-mvsx' options" } */ + return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mcpu=power9 and -mvsx' options" } */ } -- 2.47.3
