Re: [PATCH 1/4] RISC-V: Add APEX backend machine description and constraints

[Kito Cheng]

> +(define_expand "riscv_arcv_apex_void_ftype_src0_v"
> +  [(unspec_volatile [(match_operand:SI 0 "const_int_operand")
> +    (match_operand 1 "nonmemory_operand")]
> +       UNSPEC_ARCV_APEX_VOID_SRC0_V)]
> +  ""
> +{
> +  emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
> +                                gen_rtvec (2, operands[0],
> +                                              operands[1]),
> +                                UNSPEC_ARCV_APEX_VOID_SRC0_V));
> +  DONE;
> +})


You only some think like this since it's same as what you emit via
emit_insn unless I'm mistaken?

(define_expand "riscv_arcv_apex_void_ftype_src0_v"
  [(unspec_volatile [(match_operand:SI 0 "const_int_operand")
    (match_operand 1 "nonmemory_operand")]
       UNSPEC_ARCV_APEX_VOID_SRC0_V)]
  ""
{
})

And same for all other define_expand pattern