From: Robin Dapp <[email protected]>

Building upon Richard's register filters, this patch series introduces filters 
that can base their filtering decision on a second operand:  The constrained 
operand (the "dependent" operand), and the "referenced" operand.
This allows e.g. to constrain the dependent operand relative to the mode of an 
output operand.  For RISC-V, a typical example is when a source of a widening 
vector instruction must either not overlap the destination at all or only a 
specific subreg of the destination.

A major difference to register filters is that dependent filters are dynamic 
and can therefore be significantly heavier in compile-time.  Also, by their
nature, they are order-dependent, influencing greedy coloring heuristics.

I haven't observed a compile-time hit across SPEC but so far only tested with
a single dependent filter.  I wouldn't expect too many dynamic filters active 
at the same time and still added a simple caching scheme.

The series is organized similarly to Richard's.  First, the gen plumbing, then 
recog.  The lra change should be sufficient for correctness and the ira patch 
improves register allocation.  The RA changes have been slightly 
"whack-a-mole"y.  I just added handling until I got the expected results.
Further input and ideas towards a more comprehensive solution appreciated.  
Rather than keeping it to myself for much longer (sorry Richard for CC'ing you 
again while backprop is still in flight, but I figured you're interested), I 
now decided to send out the current version.

The series was regtested and bootstrapped on x86, power10, and aarch64.
Regtested on riscv64.

Robin Dapp (5):
  genpreds: Dependent, dynamic register filters.
  recog: Handle dependent filters.
  lra: Support dependent filters.
  RISC-V: Example dependent filter for widen overlap.
  ira: Add dependent filter handling.

 gcc/config/riscv/constraints.md               |   8 +
 gcc/config/riscv/riscv-protos.h               |   2 +
 gcc/config/riscv/riscv.cc                     |  35 +++
 gcc/config/riscv/vector.md                    |  16 +-
 gcc/doc/md.texi                               |  19 +-
 gcc/doc/tm.texi                               |   3 +
 gcc/doc/tm.texi.in                            |   3 +
 gcc/genconfig.cc                              |   1 +
 gcc/genpreds.cc                               | 166 ++++++++++++-
 gcc/gensupport.cc                             |  37 ++-
 gcc/gensupport.h                              |   2 +
 gcc/ira-build.cc                              |  25 ++
 gcc/ira-color.cc                              |  63 ++++-
 gcc/ira-conflicts.cc                          |  52 ++++-
 gcc/ira-int.h                                 |  29 +++
 gcc/ira-lives.cc                              |  92 ++++++++
 gcc/ira.cc                                    |   1 +
 gcc/lra-assigns.cc                            |  23 ++
 gcc/lra-constraints.cc                        | 221 ++++++++++++++++++
 gcc/lra-int.h                                 |  22 ++
 gcc/lra.cc                                    |   8 +-
 gcc/lra.h                                     |   3 +
 gcc/recog.cc                                  |  33 ++-
 gcc/recog.h                                   |  16 ++
 gcc/rtl.def                                   |  12 +-
 .../gcc.target/riscv/rvv/base/pr112431-4.c    |   2 +-
 .../gcc.target/riscv/rvv/base/pr112431-5.c    |   2 +-
 .../gcc.target/riscv/rvv/base/pr112431-6.c    |   2 +-
 28 files changed, 862 insertions(+), 36 deletions(-)

-- 
2.53.0

Reply via email to