diff --git a/gcc/config/sh/sh-mem.cc b/gcc/config/sh/sh-mem.cc
index 980b55a3a6c..591bdabad6a 100644
--- a/gcc/config/sh/sh-mem.cc
+++ b/gcc/config/sh/sh-mem.cc
@@ -273,7 +273,7 @@ sh_expand_cmpstr (rtx *operands)
add_int_reg_note (jump, REG_BR_PROB, prob_likely);
/* end loop. */
- /* Fallthu, substract words. */
+ /* Fallthu, subtract words. */
if (TARGET_LITTLE_ENDIAN)
{
rtx low_1 = gen_lowpart (HImode, tmp1);
diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index 3fe22d389b1..1dbc63f177e 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -847,7 +847,7 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH4A;
}
- /* User/priviledged mode is supported only on SH3* and SH4*.
+ /* User/privileged mode is supported only on SH3* and SH4*.
Disable it for everything else. */
if (!TARGET_SH3 && TARGET_USERMODE)
TARGET_USERMODE = false;
@@ -3291,7 +3291,7 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
int outer_code,
&& XEXP (x, 1) == const1_rtx
&& CONST_INT_P (XEXP (x, 2))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
- /* Check that the xor constaint overlaps with the extracted bit. */
+ /* Check that the xor constraint overlaps with the extracted bit. */
&& (INTVAL (XEXP (XEXP (x, 0), 1)) & (1LL << INTVAL (XEXP (x, 2)))))
{
*total = 1; //COSTS_N_INSNS (1);
@@ -5728,7 +5728,7 @@ fixup_addr_diff_vecs (rtx_insn *first)
break;
}
/* FIXME: This is a bug in the optimizer, but it seems harmless
- to just avoid panicing. */
+ to just avoid panicking. */
if (!prev)
continue;
@@ -7298,7 +7298,7 @@ sh_expand_epilogue (bool sibcall_p)
else
break;
- /* Use movml when all banked register are poped. */
+ /* Use movml when all banked register are popped. */
if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
use_movml = true;
}
@@ -11451,7 +11451,7 @@ sh_legitimize_address_displacement (rtx *offset1, rtx
*offset2,
return false;
}
-/* Return true if movsf insn should be splited with an additional
+/* Return true if movsf insn should be split with an additional
register. */
bool
sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2)
@@ -11552,7 +11552,7 @@ sh_can_use_simple_return_p (void)
if (! reload_completed || frame_pointer_needed)
return false;
- /* Moving prologue around does't reduce the size. */
+ /* Moving prologue around doesn't reduce the size. */
if (optimize_function_for_size_p (cfun))
return false;
@@ -11719,7 +11719,7 @@ sh_find_equiv_gbr_addr (rtx_insn* insn, rtx mem)
{
/* If GBR is marked as call clobbered we bail out if we see a call.
FIXME: Actually should check if this mem refers to the gbr value
- before or after the call. If there is a store_gbr preceeding this
+ before or after the call. If there is a store_gbr preceding this
mem, it's safe to use GBR for this mem.
If GBR is not marked as call clobbered, but there is some other
@@ -11884,7 +11884,7 @@ sh_check_add_incdec_notes (rtx_insn* i)
return i;
}
-/* Given a move insn destiation and a source, make sure that the move source
+/* Given a move insn destination and a source, make sure that the move source
operand is not a post-inc mem load with the same address reg as the
destination. Returns the modified source operand with the post-inc removed
if necessary. */
@@ -12251,7 +12251,7 @@ private:
};
/* Given an rtx x, determine whether the expression can be used to create
- an insn that calulates x and stores the result in the T bit.
+ an insn that calculates x and stores the result in the T bit.
This is used by the 'treg_set_expr' predicate to construct insns sequences
where T bit results are fed into other insns, such as addc, subc, negc
insns.
@@ -12260,7 +12260,7 @@ private:
distinguish between 'positive' and 'negative' forms. For now this has to
be done in the preparation code. We could also introduce
'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write
- two different patterns for the 'postive' and 'negative' forms. However,
+ two different patterns for the 'positive' and 'negative' forms. However,
the total amount of lines of code seems to be about the same and the
'{pos|neg}_treg_set_expr' predicates would be more expensive, because the
recog function would need to look inside the expression by temporarily
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 07f8968b0f5..98790f6f7fe 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -823,7 +823,7 @@
;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
;; Try to fix that in the split1 pass by looking for the previous set
-;; of the tested op. Also see if there is a preceeding sign/zero
+;; of the tested op. Also see if there is a preceding sign/zero
;; extension that can be avoided.
(define_split
[(set (reg:SI T_REG)
@@ -854,7 +854,7 @@
&& !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
{
if (dump_file)
- fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
+ fprintf (dump_file, "cmpeqsi_t: found preceding and in insn %d\n",
INSN_UID (op.insn));
if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
@@ -1653,7 +1653,7 @@
(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
-;; The tree optimiziers canonicalize
+;; The tree optimizers canonicalize
;; reg + (reg & 1)
;; into
;; (reg + 1) & -2
@@ -5318,7 +5318,7 @@
})
;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
-;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
+;; 0xf0000008, we get the low-order bits *1*00 (binary), which fits
;; the requirement *1*00 for associative address writes. The alignment of
;; %0 implies that its least significant bit is cleared,
;; thus we clear the V bit of a matching entry if there is one.
@@ -5438,11 +5438,11 @@
;; placed into delay slots. Since there is no QImode PC relative load, the
;; Q constraint and general_movsrc_operand will reject it for QImode.
;; The Sid/Ssd alternatives should come before Sdd in order to avoid
-;; a preference of using r0 als the register operand for addressing modes
+;; a preference of using r0 as the register operand for addressing modes
;; other than displacement addressing.
;; The Sdd alternatives allow only r0 as register operand, even though on
;; SH2A any register could be allowed by switching to a 32 bit insn.
-;; Generally sticking to the r0 is preferrable, since it generates smaller
+;; Generally sticking to the r0 is preferable, since it generates smaller
;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
(define_insn "*mov<mode>"
[(set (match_operand:QIHI 0 "general_movdst_operand"
@@ -10892,7 +10892,7 @@
;; to be one. It tries to convert a sequence such as
;; movt r2 -> movt r2
;; movt r13 mov r2,r13
-;; This gives the schduler a bit more freedom to hoist a following
+;; This gives the scheduler a bit more freedom to hoist a following
;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has
;; better chances for parallel execution.
;; We can do this with a peephole2 pattern, but then the cprop_hardreg
diff --git a/gcc/config/sh/sh4-300.md b/gcc/config/sh/sh4-300.md
index df128b7fff8..0f31ed85a4e 100644
--- a/gcc/config/sh/sh4-300.md
+++ b/gcc/config/sh/sh4-300.md
@@ -269,7 +269,7 @@
(eq_attr "type" "arith3"))
"sh4_300_issue,all*4")
-;; arith3b insns without brach redirection make use of the 0-offset 0-latency
+;; arith3b insns without branch redirection make use of the 0-offset 0-latency
;; branch feature, and thus schedule the same no matter if the branch is taken
;; or not. If the branch is redirected, the taken branch might take longer,
;; but then, we don't have to take the next branch.
diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc
index df820d7d39c..05225365b99 100644
--- a/gcc/config/sh/sh_treg_combine.cc
+++ b/gcc/config/sh/sh_treg_combine.cc
@@ -57,7 +57,7 @@ checking whether the ccreg is set before the conditional
branch
by testing another register for != 0, which was set by a ccreg store.
This can be optimized by eliminating the redundant comparison and
inverting the branch condition. There can be multiple comparisons in
-different basic blocks that all end up in the redunant test insn before the
+different basic blocks that all end up in the redundant test insn before the
conditional branch. Some example RTL ...
Example 1)
@@ -1085,7 +1085,7 @@ sh_treg_combine::try_combine_comparisons (cbranch_trace&
trace,
{
int i_empty_count = i->setcc.empty () + i->cstore.empty ();
- // A completly empty entry is OK (could be the BB of the cbranch).
+ // A completely empty entry is OK (could be the BB of the cbranch).
if (i_empty_count == 2)
continue;
@@ -1261,7 +1261,7 @@ sh_treg_combine::try_eliminate_cstores (cbranch_trace&
trace,
for (std::list<bb_entry>::const_iterator i = trace.bb_entries.begin ();
i != trace.bb_entries.end (); ++i)
{
- // A completly empty entry is OK (could be the BB of the cbranch).
+ // A completely empty entry is OK (could be the BB of the cbranch).
if (i->setcc.empty () && i->cstore.empty ())
continue;
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 2eca3accbc8..b0b412b3d9d 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -42,7 +42,7 @@
;; Hardware Atomics (-matomic-model=hard-llcs; SH4A only)
;;
;; Hardware atomics implement all atomic operations using the 'movli.l' and
-;; 'movco.l' instructions that are availble on SH4A. On multi-core hardware
+;; 'movco.l' instructions that are available on SH4A. On multi-core hardware
;; configurations hardware atomics is the only safe mode.
;; However, it can also be safely used on single-core configurations.
;; Since these instructions operate on SImode memory only, QImode and HImode
@@ -196,7 +196,7 @@
[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
;;------------------------------------------------------------------------------
-;; comapre and swap
+;; compare and swap
;; Only the hard_llcs SImode patterns can use an I08 for the comparison
;; or for the new swapped in value.
--
2.43.0
