Hi gcc-patches mailing list, Karl Meakin via Sourceware Forge <[email protected]> has requested that the following forgejo pull request be published on the mailing list.
Created on: 2026-05-13 15:39:36+00:00 Latest update: 2026-05-28 14:23:04+00:00 Changes: 117 changed files, 20781 additions, 16797 deletions Head revision: karmea01/gcc-TEST ref dsg/karmea01/neon-port commit 11538878a42726b004c04bcace9b13b1c4d507f7 Base revision: gcc/gcc-TEST ref trunk commit 4e6f6b34d6fded28c0a8662c782757073e274507 r17-903-g4e6f6b34d6fded Merge base: 4e6f6b34d6fded28c0a8662c782757073e274507 Full diff url: https://forge.sourceware.org/gcc/gcc-TEST/pulls/158.diff Discussion: https://forge.sourceware.org/gcc/gcc-TEST/pulls/158 Requested Reviewers: rdfm, pinskia This patch is a proof of concept patch which ports a few NEON intrinsics (intrinsics defined in `arm_neon.h`) to the "pragma-based" framework used by SVE/SME intrinsics. If successful, I will follow up with further patches porting the rest. tested with `make check` changelog: * v1: Initial revision * v2: Appease `check_GNU_style.py` * v3: Drop unrelated `.editorconfig` changes which were included by mistake * v4: * Address review comments * Move reformatting of `config.gcc` into its own commit. * Merge `aarch64-neon-builtins.cc` into `aarch64-sve-builtins.cc` and rename it to `aarch64-acle-builtins.cc` * v5: Fix codegen for big-endian targets * v6 Improve codegen for `FEAT_SHA3` intrinsics (`veor3`, `vbcax`, `vrax1` and `vxar`) at `-O0`. Changed files: - A: gcc/config/aarch64/aarch64-acle-builtins.cc - A: gcc/config/aarch64/aarch64-acle-builtins.h - A: gcc/config/aarch64/aarch64-neon-builtins-base.cc - A: gcc/config/aarch64/aarch64-neon-builtins-base.def - A: gcc/config/aarch64/aarch64-neon-builtins-base.h - A: gcc/config/aarch64/aarch64-neon-builtins-functions.h - A: gcc/config/aarch64/aarch64-neon-builtins-shapes.cc - A: gcc/config/aarch64/aarch64-neon-builtins-shapes.h - A: gcc/config/aarch64/aarch64-neon-builtins.cc - A: gcc/config/aarch64/aarch64-neon-builtins.def - A: gcc/config/aarch64/aarch64-neon-builtins.h - A: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_indices.c - A: gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp - A: gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h - A: gcc/testsuite/gcc.target/aarch64/neon/vadd.c - A: gcc/testsuite/gcc.target/aarch64/neon/vand.c - A: gcc/testsuite/gcc.target/aarch64/neon/vbcax.c - A: gcc/testsuite/gcc.target/aarch64/neon/vbic.c - A: gcc/testsuite/gcc.target/aarch64/neon/vbsl.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcls.c - A: gcc/testsuite/gcc.target/aarch64/neon/vclz.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcnt.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcombine.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/vcreate.c - A: gcc/testsuite/gcc.target/aarch64/neon/vdup.c - A: gcc/testsuite/gcc.target/aarch64/neon/vdup_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/veor.c - A: gcc/testsuite/gcc.target/aarch64/neon/veor3.c - A: gcc/testsuite/gcc.target/aarch64/neon/vext.c - A: gcc/testsuite/gcc.target/aarch64/neon/vget_high.c - A: gcc/testsuite/gcc.target/aarch64/neon/vget_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/vget_low.c - A: gcc/testsuite/gcc.target/aarch64/neon/vmov_n.c - A: gcc/testsuite/gcc.target/aarch64/neon/vmvn.c - A: gcc/testsuite/gcc.target/aarch64/neon/vorn.c - A: gcc/testsuite/gcc.target/aarch64/neon/vorr.c - A: gcc/testsuite/gcc.target/aarch64/neon/vrax1.c - A: gcc/testsuite/gcc.target/aarch64/neon/vrbit.c - A: gcc/testsuite/gcc.target/aarch64/neon/vreinterpret.c - A: gcc/testsuite/gcc.target/aarch64/neon/vrev.c - A: gcc/testsuite/gcc.target/aarch64/neon/vset_lane.c - A: gcc/testsuite/gcc.target/aarch64/neon/vtrn.c - A: gcc/testsuite/gcc.target/aarch64/neon/vuzp.c - A: gcc/testsuite/gcc.target/aarch64/neon/vxar.c - A: gcc/testsuite/gcc.target/aarch64/neon/vzip.c - A: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_indices.c - D: gcc/config/aarch64/aarch64-sve-builtins.cc - D: gcc/config/aarch64/aarch64-sve-builtins.h - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_2.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s8_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u16_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u32_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c - D: gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c - M: gcc/config.gcc - M: gcc/config/aarch64/aarch64-builtins.cc - M: gcc/config/aarch64/aarch64-builtins.h - M: gcc/config/aarch64/aarch64-c.cc - M: gcc/config/aarch64/aarch64-protos.h - M: gcc/config/aarch64/aarch64-simd-builtins.def - M: gcc/config/aarch64/aarch64-simd-pragma-builtins.def - M: gcc/config/aarch64/aarch64-simd.md - M: gcc/config/aarch64/aarch64-sve-builtins-base.cc - M: gcc/config/aarch64/aarch64-sve-builtins-base.h - M: gcc/config/aarch64/aarch64-sve-builtins-functions.h - M: gcc/config/aarch64/aarch64-sve-builtins-shapes.cc - M: gcc/config/aarch64/aarch64-sve-builtins-shapes.h - M: gcc/config/aarch64/aarch64-sve-builtins-sme.cc - M: gcc/config/aarch64/aarch64-sve-builtins-sme.h - M: gcc/config/aarch64/aarch64-sve-builtins-sve2.cc - M: gcc/config/aarch64/aarch64-sve-builtins-sve2.h - M: gcc/config/aarch64/aarch64-sve-builtins.def - M: gcc/config/aarch64/aarch64.cc - M: gcc/config/aarch64/aarch64.md - M: gcc/config/aarch64/arm_neon.h - M: gcc/config/aarch64/iterators.md - M: gcc/config/aarch64/t-aarch64 - M: gcc/testsuite/g++.target/aarch64/lane-bound-1.C - M: gcc/testsuite/g++.target/aarch64/pr103147-6.C - M: gcc/testsuite/g++.target/aarch64/pr117048.C - M: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c - M: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_vect_copy_lane_1.c - M: gcc/testsuite/gcc.target/aarch64/lane-bound-3.c - M: gcc/testsuite/gcc.target/aarch64/pr103147-6.c - M: gcc/testsuite/gcc.target/aarch64/pr113573.c - M: gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_6.c - M: gcc/testsuite/gcc.target/aarch64/simd/mf8_data_2.c - M: gcc/testsuite/gcc.target/aarch64/simd/vset_lane_s16_const_1.c - M: gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c - M: gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c - M: gcc/testsuite/gcc.target/aarch64/target_attr_10.c - M: gcc/testsuite/gcc.target/aarch64/vmov_n_1.c Karl Meakin (7): aarch64: Reformat `config.gcc` aarch64: Rename `aarch64-sve-builtins` to `aarch64-acle-builtins` aarch64: Port NEON add intrinsics to pragma-based framework aarch64: Port NEON vector manipulation intrinsics to pragma-based framework aarch64: Port NEON bit manipulation intrinsics to pragma-based framework aarch64: Port NEON permutation intrinsics to pragma-based framework aarch64: Port NEON reinterpret intrinsics to pragma-based framework gcc/config.gcc | 40 +- ...e-builtins.cc => aarch64-acle-builtins.cc} | 955 +- ...sve-builtins.h => aarch64-acle-builtins.h} | 1000 +- gcc/config/aarch64/aarch64-builtins.cc | 548 +- gcc/config/aarch64/aarch64-builtins.h | 1 + gcc/config/aarch64/aarch64-c.cc | 18 +- .../aarch64/aarch64-neon-builtins-base.cc | 834 + .../aarch64/aarch64-neon-builtins-base.def | 147 + .../aarch64/aarch64-neon-builtins-base.h | 29 + .../aarch64/aarch64-neon-builtins-functions.h | 29 + .../aarch64/aarch64-neon-builtins-shapes.cc | 132 + .../aarch64/aarch64-neon-builtins-shapes.h | 29 + gcc/config/aarch64/aarch64-neon-builtins.cc | 49 + gcc/config/aarch64/aarch64-neon-builtins.def | 40 + gcc/config/aarch64/aarch64-neon-builtins.h | 23 + gcc/config/aarch64/aarch64-protos.h | 5 +- gcc/config/aarch64/aarch64-simd-builtins.def | 36 - .../aarch64/aarch64-simd-pragma-builtins.def | 105 - gcc/config/aarch64/aarch64-simd.md | 21 +- .../aarch64/aarch64-sve-builtins-base.cc | 16 +- .../aarch64/aarch64-sve-builtins-base.h | 2 +- .../aarch64/aarch64-sve-builtins-functions.h | 2 +- .../aarch64/aarch64-sve-builtins-shapes.cc | 47 +- .../aarch64/aarch64-sve-builtins-shapes.h | 2 +- .../aarch64/aarch64-sve-builtins-sme.cc | 8 +- gcc/config/aarch64/aarch64-sve-builtins-sme.h | 2 +- .../aarch64/aarch64-sve-builtins-sve2.cc | 8 +- .../aarch64/aarch64-sve-builtins-sve2.h | 2 +- gcc/config/aarch64/aarch64-sve-builtins.def | 11 + gcc/config/aarch64/aarch64.cc | 40 +- gcc/config/aarch64/aarch64.md | 6 - gcc/config/aarch64/arm_neon.h | 22960 ++++++---------- gcc/config/aarch64/iterators.md | 2 +- gcc/config/aarch64/t-aarch64 | 43 +- .../g++.target/aarch64/lane-bound-1.C | 2 +- gcc/testsuite/g++.target/aarch64/pr103147-6.C | 1 + gcc/testsuite/g++.target/aarch64/pr117048.C | 2 +- .../aarch64/advsimd-intrinsics/bf16_dup.c | 7 +- .../bf16_vect_copy_lane_1.c | 3 +- .../vcopy_lane_bf16_indices_1.c | 18 - .../vcopy_lane_bf16_indices_2.c | 18 - .../advsimd-intrinsics/vcopy_lane_indices.c | 68 + .../vcopy_laneq_bf16_indices_1.c | 17 - .../vcopy_laneq_bf16_indices_2.c | 17 - .../vcopyq_lane_bf16_indices_1.c | 17 - .../vcopyq_lane_bf16_indices_2.c | 17 - .../vcopyq_laneq_bf16_indices_1.c | 17 - .../vcopyq_laneq_bf16_indices_2.c | 17 - .../gcc.target/aarch64/lane-bound-3.c | 4 +- .../gcc.target/aarch64/neon/aarch64-neon.exp | 43 + .../gcc.target/aarch64/neon/arm_neon_test.h | 24 + gcc/testsuite/gcc.target/aarch64/neon/vadd.c | 203 + gcc/testsuite/gcc.target/aarch64/neon/vand.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vbcax.c | 60 + gcc/testsuite/gcc.target/aarch64/neon/vbic.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vbsl.c | 214 + gcc/testsuite/gcc.target/aarch64/neon/vcls.c | 88 + gcc/testsuite/gcc.target/aarch64/neon/vclz.c | 88 + gcc/testsuite/gcc.target/aarch64/neon/vcnt.c | 25 + .../gcc.target/aarch64/neon/vcombine.c | 120 + .../gcc.target/aarch64/neon/vcopy_lane.c | 438 + .../gcc.target/aarch64/neon/vcreate.c | 119 + gcc/testsuite/gcc.target/aarch64/neon/vdup.c | 226 + .../gcc.target/aarch64/neon/vdup_lane.c | 647 + gcc/testsuite/gcc.target/aarch64/neon/veor.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/veor3.c | 60 + gcc/testsuite/gcc.target/aarch64/neon/vext.c | 216 + .../gcc.target/aarch64/neon/vget_high.c | 116 + .../gcc.target/aarch64/neon/vget_lane.c | 449 + .../gcc.target/aarch64/neon/vget_low.c | 100 + .../gcc.target/aarch64/neon/vmov_n.c | 212 + gcc/testsuite/gcc.target/aarch64/neon/vmvn.c | 102 + gcc/testsuite/gcc.target/aarch64/neon/vorn.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vorr.c | 116 + gcc/testsuite/gcc.target/aarch64/neon/vrax1.c | 11 + gcc/testsuite/gcc.target/aarch64/neon/vrbit.c | 46 + .../gcc.target/aarch64/neon/vreinterpret.c | 3143 +++ gcc/testsuite/gcc.target/aarch64/neon/vrev.c | 311 + .../gcc.target/aarch64/neon/vset_lane.c | 234 + gcc/testsuite/gcc.target/aarch64/neon/vtrn.c | 566 + gcc/testsuite/gcc.target/aarch64/neon/vuzp.c | 566 + gcc/testsuite/gcc.target/aarch64/neon/vxar.c | 32 + gcc/testsuite/gcc.target/aarch64/neon/vzip.c | 559 + gcc/testsuite/gcc.target/aarch64/pr103147-6.c | 1 + gcc/testsuite/gcc.target/aarch64/pr113573.c | 62 +- .../aarch64/simd/fold_to_highpart_6.c | 24 +- .../gcc.target/aarch64/simd/mf8_data_2.c | 1 - .../aarch64/simd/vget_lane_f32_indices_1.c | 17 - .../aarch64/simd/vget_lane_f64_indices_1.c | 17 - .../aarch64/simd/vget_lane_indices.c | 46 + .../aarch64/simd/vget_lane_p16_indices_1.c | 17 - .../aarch64/simd/vget_lane_p8_indices_1.c | 17 - .../aarch64/simd/vget_lane_s16_indices_1.c | 17 - .../aarch64/simd/vget_lane_s32_indices_1.c | 17 - .../aarch64/simd/vget_lane_s64_indices_1.c | 17 - .../aarch64/simd/vget_lane_s8_indices_1.c | 17 - .../aarch64/simd/vget_lane_u16_indices_1.c | 17 - .../aarch64/simd/vget_lane_u32_indices_1.c | 17 - .../aarch64/simd/vget_lane_u64_indices_1.c | 17 - .../aarch64/simd/vget_lane_u8_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_f32_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_f64_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_p16_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_p8_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s16_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s32_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s64_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_s8_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u16_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u32_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u64_indices_1.c | 17 - .../aarch64/simd/vgetq_lane_u8_indices_1.c | 17 - .../aarch64/simd/vset_lane_s16_const_1.c | 2 +- .../gcc.target/aarch64/sme/inlining_10.c | 6 +- .../gcc.target/aarch64/sme/inlining_11.c | 7 +- .../gcc.target/aarch64/target_attr_10.c | 4 +- gcc/testsuite/gcc.target/aarch64/vmov_n_1.c | 2 +- 117 files changed, 20781 insertions(+), 16797 deletions(-) rename gcc/config/aarch64/{aarch64-sve-builtins.cc => aarch64-acle-builtins.cc} (87%) rename gcc/config/aarch64/{aarch64-sve-builtins.h => aarch64-acle-builtins.h} (59%) create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-base.cc create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-base.def create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-base.h create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-functions.h create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-shapes.cc create mode 100644 gcc/config/aarch64/aarch64-neon-builtins-shapes.h create mode 100644 gcc/config/aarch64/aarch64-neon-builtins.cc create mode 100644 gcc/config/aarch64/aarch64-neon-builtins.def create mode 100644 gcc/config/aarch64/aarch64-neon-builtins.h delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_bf16_indices_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_lane_indices.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopy_laneq_bf16_indices_2.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_lane_bf16_indices_2.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcopyq_laneq_bf16_indices_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vadd.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vand.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vbcax.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vbic.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vbsl.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcls.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vclz.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcnt.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcombine.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcreate.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vdup.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vdup_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/veor.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/veor3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vext.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vget_high.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vget_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vget_low.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmov_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmvn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vorn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vorr.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrax1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrbit.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vreinterpret.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrev.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vset_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vtrn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vuzp.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vxar.c create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vzip.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f32_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f64_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_indices.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p8_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s32_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s64_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s8_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u32_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u64_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u8_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f32_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f64_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p8_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s32_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s64_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s8_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u16_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u32_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c Range-diff against v5: 1: 1410016e1ee8 = 1: fecd9fba0ae6 aarch64: Reformat `config.gcc` 2: 42cce26efb4c = 2: 9e9d987c4c96 aarch64: Rename `aarch64-sve-builtins` to `aarch64-acle-builtins` 3: a68311b98751 ! 3: a6069ecc10d7 aarch64: Port NEON add intrinsics to pragma-based framework @@ gcc/config.gcc: aarch64*-*-*) extra_objs="${extra_objs} aarch64-json-tunings-printer.o" extra_objs="${extra_objs} aarch64-json-tunings-parser.o" extra_objs="${extra_objs} aarch64-narrow-gp-writes.o" -+ extra_objs="${extra_objs} aarch64-neon-builtins.o" + extra_objs="${extra_objs} aarch64-neon-builtins-base.o" + extra_objs="${extra_objs} aarch64-neon-builtins-shapes.o" @@ gcc/config/aarch64/aarch64-acle-builtins.h: function_expander::result_mode () co + +/* Used by SME instructions that always merge into ZA. */ +static const predication_index preds_za_m[] = { PRED_za_m, NUM_PREDS }; ++ ++void build_all (function_builder &b, const char *signature, ++ const function_group_info &group, ++ mode_suffix_index mode_suffix_id, ++ bool force_direct_overloads = false); } #endif @@ gcc/config/aarch64/aarch64-sve-builtins-shapes.cc: build_vs_offset (function_bui +void build_all (function_builder &b, const char *signature, const function_group_info &group, mode_suffix_index mode_suffix_id, - bool force_direct_overloads = false) +- bool force_direct_overloads = false) ++ bool force_direct_overloads) + { + for (unsigned int pi = 0; group.preds[pi] != NUM_PREDS; ++pi) + for (unsigned int gi = 0; group.groups[gi] != NUM_GROUP_SUFFIXES; ++gi) ## gcc/config/aarch64/aarch64-sve-builtins.def ## @@ @@ gcc/config/aarch64/t-aarch64: aarch64-builtins.o: $(srcdir)/config/aarch64/aarch $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/aarch64/aarch64-builtins.cc -+aaaarch64-neon-builtins-shapes.o: \ ++aarch64-neon-builtins-shapes.o: \ + $(srcdir)/config/aarch64/aarch64-neon-builtins-shapes.cc \ + $(srcdir)/config/aarch64/aarch64-neon-builtins.def \ + $(srcdir)/config/aarch64/aarch64-neon-builtins-base.def \ @@ gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp (new) +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*\[cCs\]]] \ + " -ansi -pedantic-errors -std=c23 -O3 -march=armv8-a+simd" "" + ++# Again, for big-endian targets. ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*\[cCs\]]] \ ++ " -ansi -pedantic-errors -std=c23 -O3 -march=armv8-a+simd -mbig-endian" "" ++ +# All done. +dg-finish 4: 2359419106db ! 4: 6c191ae1ce75 aarch64: Port NEON vector manipulation intrinsics to pragma-based framework @@ gcc/testsuite/gcc.target/aarch64/lane-bound-3.c __builtin_unreachable(); } - ## gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp ## -@@ gcc/testsuite/gcc.target/aarch64/neon/aarch64-neon.exp: dg-init - dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*\[cCs\]]] \ - " -ansi -pedantic-errors -std=c23 -O3 -march=armv8-a+simd" "" - -+# Again, for big-endian targets. -+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*\[cCs\]]] \ -+ " -ansi -pedantic-errors -std=c23 -O3 -march=armv8-a+simd -mbig-endian" "" -+ - # All done. - dg-finish - ## gcc/testsuite/gcc.target/aarch64/neon/arm_neon_test.h ## @@ @@ gcc/testsuite/gcc.target/aarch64/neon/vcopy_lane.c (new) +// ret + +/* -+** test_vcopy_lane_f32: { xfail { aarch64_big_endian || { any-opts mbig-endian" } } } ++** test_vcopy_lane_f32: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.s\[1\], v1\.s\[1\] +** ret +*/ +TEST_COPY_LANE (vcopy_lane_f32, float32x2_t, float32x2_t) + +/* -+** test_vcopy_lane_s32: { xfail { aarch64_big_endian || { any-opts mbig-endian" } } } ++** test_vcopy_lane_s32: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.s\[1\], v1\.s\[1\] +** ret +*/ +TEST_COPY_LANE (vcopy_lane_s32, int32x2_t, int32x2_t) + +/* -+** test_vcopy_lane_u32: { xfail { aarch64_big_endian || { any-opts mbig-endian" } } } ++** test_vcopy_lane_u32: { xfail { aarch64_big_endian || { any-opts "-mbig-endian" } } } +** ins v0\.s\[1\], v1\.s\[1\] +** ret +*/ 5: 75dcf7bfce80 ! 5: b1b4ff6e432d aarch64: Port NEON bit manipulation intrinsics to pragma-based framework @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi + gimple *fold (gimple_folder &) const override { return nullptr; } +}; + ++/* SHA3 expand to RTL at `-O0` because we want to emit one instruction for them ++ even when optimizations are disabled. */ ++ +/* EOR3 (n, m, a) = (n ^ m) ^ a. */ +class gimple_eor3 : public gimple_function_base +{ +public: + gimple *fold (gimple_folder &f) const override + { ++ if (optimize == 0) ++ return nullptr; ++ + auto n = gimple_call_arg (f.call, 0); + auto m = gimple_call_arg (f.call, 1); + auto a = gimple_call_arg (f.call, 2); @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi + // lhs = (n ^ m) ^ a + return gimple_build_assign (f.lhs, BIT_XOR_EXPR, tmp1, a); + } ++ ++ rtx expand (function_expander &e) const override ++ { ++ return e.use_exact_insn (code_for_eor3q4 (e.args[0]->mode)); ++ } +}; + +/* BCAX (n, m, a) = n ^ (m & ~a). */ @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi +public: + gimple *fold (gimple_folder &f) const override + { ++ if (optimize == 0) ++ return nullptr; ++ + auto n = gimple_call_arg (f.call, 0); + auto m = gimple_call_arg (f.call, 1); + auto a = gimple_call_arg (f.call, 2); @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi + // lhs = n ^ (m & ~a) + return gimple_build_assign (f.lhs, BIT_XOR_EXPR, n, tmp2); + } ++ ++ rtx expand (function_expander &e) const override ++ { ++ return e.use_exact_insn (code_for_bcaxq4 (e.args[0]->mode)); ++ } +}; + +/* RAX1 (n, m) = n ^ rotl (m, splat (1)). */ @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi +public: + gimple *fold (gimple_folder &f) const override + { ++ if (optimize == 0) ++ return nullptr; ++ + auto n = gimple_call_arg (f.call, 0); + auto m = gimple_call_arg (f.call, 1); + auto arg_type = TREE_TYPE (n); @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi + // lhs = n ^ rotl (m, 1) + return gimple_build_assign (f.lhs, BIT_XOR_EXPR, n, tmp1); + } ++ ++ rtx expand (function_expander &e) const override ++ { ++ return e.use_exact_insn (CODE_FOR_aarch64_rax1qv2di); ++ } +}; + +/* XAR (n, m, imm6) = rotr (n ^ m, imm6). */ @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi +public: + gimple *fold (gimple_folder &f) const override + { ++ if (optimize == 0) ++ return nullptr; ++ + auto n = gimple_call_arg (f.call, 0); + auto m = gimple_call_arg (f.call, 1); + auto imm6 = gimple_call_arg (f.call, 2); @@ gcc/config/aarch64/aarch64-neon-builtins-base.cc: struct gimple_dup_lane : publi + // lhs = rotr (n ^ m, imm6) + return gimple_build_assign (f.lhs, RROTATE_EXPR, tmp1, imm6); + } ++ ++ rtx expand (function_expander &e) const override ++ { ++ return e.use_exact_insn (CODE_FOR_aarch64_xarqv2di); ++ } +}; + +/* For intrinsics that map to a single GIMPLE IFN with no argument @@ gcc/config/aarch64/aarch64-simd-pragma-builtins.def: ENTRY_FMA_FPM (vmlalltb, f3 ## gcc/config/aarch64/aarch64-simd.md ## @@ - [(set_attr "type" "neon_rev<q>")] - ) + "TARGET_SIMD" + "") -(define_insn "aarch64_rbit<mode><vczle><vczbe>" +(define_insn "@aarch64_rbit<mode><vczle><vczbe>" @@ gcc/config/aarch64/aarch64-simd.md (bitreverse:VB (match_operand:VB 1 "register_operand" "w")))] "TARGET_SIMD" @@ + + ;; sha3 + +-(define_insn "eor3q<mode>4" ++(define_insn "@eor3q<mode>4" + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (xor:VDQ_I + (xor:VDQ_I +@@ [(set_attr "type" "crypto_sha3")] ) +-(define_insn "aarch64_rax1qv2di" +;; matches 'Vd = Vn ^ rotl (Vm, splat (1))' - (define_insn "aarch64_rax1qv2di" ++(define_insn "*aarch64_rax1qv2di" [(set (match_operand:V2DI 0 "register_operand" "=w") (xor:V2DI (rotate:V2DI @@ gcc/config/aarch64/aarch64-simd.md - (const_int 1)) + (match_operand:V2DI 3 "aarch64_simd_lshift_imm" "Dl")) (match_operand:V2DI 1 "register_operand" "w")))] -- "TARGET_SHA3" + "TARGET_SHA3 && INTVAL (unwrap_const_vec_duplicate (operands[3])) == 1" ++ "rax1\\t%0.2d, %1.2d, %2.2d" ++ [(set_attr "type" "crypto_sha3")] ++) ++ ++(define_insn "aarch64_rax1qv2di" ++ [(match_operand:V2DI 0 "register_operand" "=w") ++ (match_operand:V2DI 1 "register_operand" "w") ++ (match_operand:V2DI 2 "register_operand" "w")] + "TARGET_SHA3" "rax1\\t%0.2d, %1.2d, %2.2d" [(set_attr "type" "crypto_sha3")] +@@ + } ) + +-(define_insn "bcaxq<mode>4" ++(define_insn "@bcaxq<mode>4" + [(set (match_operand:VDQ_I 0 "register_operand" "=w") + (xor:VDQ_I + (and:VDQ_I @@ [ w , 0 , w , w ] <insn>\t%0.<Vtype>, %2.16b, %3.16b } @@ gcc/testsuite/gcc.target/aarch64/neon/vxar.c (new) +uint64x2_t test_vxarq_u64_63 (uint64x2_t a, uint64x2_t b) { return vxarq_u64 (a, b, 63); } \ No newline at end of file - ## gcc/testsuite/gcc.target/aarch64/sha3_1.c ## -@@ - /* { dg-do compile } */ --/* { dg-options "-march=armv8.2-a+sha3" } */ -+/* { dg-options "-O1 -march=armv8.2-a+sha3" } */ - - #include "sha3.h" - - - ## gcc/testsuite/gcc.target/aarch64/sha3_2.c ## -@@ - /* { dg-do compile } */ --/* { dg-options "-march=armv8.3-a+sha3" } */ -+/* { dg-options "-O1 -march=armv8.3-a+sha3" } */ - - #include "sha3.h" - - - ## gcc/testsuite/gcc.target/aarch64/sha3_3.c ## -@@ - /* { dg-do compile } */ --/* { dg-options "-march=armv8.4-a+sha3" } */ -+/* { dg-options "-O1 -march=armv8.4-a+sha3" } */ - - #include "sha3.h" - - ## gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c ## @@ gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c: call_vadd () neon[4] = vaddq_u8 (neon[5], neon[6]); 6: c6fb10d719c6 = 6: b916e0a0be8c aarch64: Port NEON permutation intrinsics to pragma-based framework 7: a20919e47347 = 7: 11538878a427 aarch64: Port NEON reinterpret intrinsics to pragma-based framework -- 2.54.0
