This patch proceeds converting insns with explicit hard registers to
hard-reg constraints, this time for FMUL, FMULS and FMULSU instructions
resp. their libgcc calls when no MUL is supported.
One question I have for Stefan:
===============================
The patch handles two orthogonal cases:
A) Operation is commutative (fmul, fmuls) or not (fmulsu).
B) Core supports MUL (use fmul* instruction) or doesn't support
MUL (generate transparent libgcc call).
I have tried two approaches to model commutativity of the inputs
in the libgcc case. These are the constraint alternatives with
hard-regs:
1) Using the "%" constraint modifier like:
"={r22}" ;; output
"%{r24}" ;; 1st input
"{r25}" ;; 2nd input
2) Using two constraint alternatives like:
"={r22},{r22}" ;; output
"{r24},{r25}" ;; 1st input
"{r25},{r24}" ;; 2nd input
Neither of which is working, i.e. RA always picks the first alternative.
Are there plans to implement this?
If yes, then what way to go? Using "%" is much more natural IMHO, and it
allows for a neat, compact and intuitive description. I would retain
the patch until the work is upstream, and then use the way as you
recommend.
If not, I would just remove any attempts that try to exploit commutative
operations and add a respective comment.
I have attached a test case fmul.c.
$ avr-gcc fmul.c -S -Os -mmcu=avr4 # takes the MUL route.
$ avr-gcc fmul.c -S -Os -mmcu=avr2 # takes the no-MUL route.
It has this test case:
uint16_t gun2 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmul (b, a);
}
which in the avr2 no-MUL path swaps r24 and r25, even though the
operands of fmul commute and the patch tries to cater for that:
gun2:
/* #APP */
;; r24 r25
/* #NOAPP */
-> mov r18,r25 ; 20 [c=4 l=1] movqi_insn/0
-> mov r25,r24 ; 21 [c=4 l=1] movqi_insn/0
-> mov r24,r18 ; 22 [c=4 l=1] movqi_insn/0
rcall __fmul ; 23 [c=8 l=1] *fmul.call/0
mov r24,r22 ; 29 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 30 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 27 [c=0 l=1] return
For Denis:
==========
The patch is for trunk. Ok with the changes as from above?
Johann
--
AVR: ad target/121343 - Use hard-reg constraints in FMUL[S[U]] insns.
PR target/121343
gcc/
* config/avr/avr.md (FMUL): New int iterator.
(fmul, fmul_X, fmul_1, fmul_2): New int attributes.
(fmul, fmuls, fmulsu): Turn from expander to insn_and_split.
(fmul_insn, fmuls_insn, fmulsu_insn): Remove.
The effect of the patch on avr.md is as follows:
(define_int_iterator FMUL [UNSPEC_FMUL UNSPEC_FMULS UNSPEC_FMULSU])
(define_int_attr fmul [(UNSPEC_FMUL "fmul") (UNSPEC_FMULS "fmuls") (UNSPEC_FMULSU
"fmulsu")])
(define_int_attr fmul_X [(UNSPEC_FMUL "%") (UNSPEC_FMULS "%") (UNSPEC_FMULSU
"")])
(define_int_attr fmul_1 [(UNSPEC_FMUL "{r25}") (UNSPEC_FMULS "{r25}") (UNSPEC_FMULSU
"{r24}")])
(define_int_attr fmul_2 [(UNSPEC_FMUL "{r24}") (UNSPEC_FMULS "{r24}") (UNSPEC_FMULSU
"{r25}")])
;; "fmul" "fmuls" "fmulsu"
(define_insn_and_split "<fmul>"
[(set (match_operand:HI 0 "register_operand" "={r22},{r22}
,r")
(unspec:HI [(match_operand:QI 1 "register_operand"
"<fmul_X>{r24},<fmul_1>,a")
(match_operand:QI 2 "register_operand"
"{r25},<fmul_2>,a")]
FMUL))
(clobber (match_scratch:HI 3 "={r24},{r24}
,X"))]
""
"#"
"&& reload_completed"
[(scratch)]
{ DONE_ADD_CCC }
[(set_attr "isa" "no_mul,no_mul,mul")])
;; "*fmul.call" "*fmuls.call" "*fmulsu.call"
(define_insn "*<fmul>.call"
[(set (reg:HI 22)
(unspec:HI [(match_operand:QI 0 "register_operand" "{r24},<fmul_1>")
(match_operand:QI 1 "register_operand" "{r25},<fmul_2>")]
FMUL))
(clobber (reg:HI 24))
(clobber (reg:CC REG_CC))]
"!AVR_HAVE_MUL && reload_completed"
"%~call __<fmul>"
[(set_attr "type" "xcall")])
;; "*fmul_insn" "*fmuls_insn" "*fmulsu_insn"
(define_insn "*<fmul>_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
(unspec:HI [(match_operand:QI 1 "register_operand" "<fmul_X>a")
(match_operand:QI 2 "register_operand" "a")]
FMUL))
(clobber (scratch:HI))
(clobber (reg:CC REG_CC))]
"AVR_HAVE_MUL && reload_completed"
"<fmul> %1,%2
movw %0,r0
clr __zero_reg__"
[(set_attr "length" "3")])
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 81722e1dbf0..6a36c8ae30e 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -9126,203 +9126,54 @@ (define_insn "*wdr"
[(set_attr "length" "1")])
;; FMUL
-(define_expand "fmul"
- [(set (reg:QI 24)
- (match_operand:QI 1 "register_operand" ""))
- (set (reg:QI 25)
- (match_operand:QI 2 "register_operand" ""))
- (parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMUL))
- (clobber (reg:HI 24))])
- (set (match_operand:HI 0 "register_operand" "")
- (reg:HI 22))]
- ""
- {
- if (AVR_HAVE_MUL)
- {
- emit_insn (gen_fmul_insn (operand0, operand1, operand2));
- DONE;
- }
- avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
- })
-
-(define_insn_and_split "fmul_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (unspec:HI [(match_operand:QI 1 "register_operand" "a")
- (match_operand:QI 2 "register_operand" "a")]
- UNSPEC_FMUL))]
- "AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(scratch)]
- { DONE_ADD_CCC })
-
-(define_insn "*fmul_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (unspec:HI [(match_operand:QI 1 "register_operand" "a")
- (match_operand:QI 2 "register_operand" "a")]
- UNSPEC_FMUL))
- (clobber (reg:CC REG_CC))]
- "AVR_HAVE_MUL && reload_completed"
- "fmul %1,%2
- movw %0,r0
- clr __zero_reg__"
- [(set_attr "length" "3")])
-
-(define_insn_and_split "*fmul.call_split"
- [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMUL))
- (clobber (reg:HI 24))]
- "!AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(scratch)]
- { DONE_ADD_CCC })
-
-(define_insn "*fmul.call"
- [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMUL))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))]
- "!AVR_HAVE_MUL && reload_completed"
- "%~call __fmul"
- [(set_attr "type" "xcall")])
-
;; FMULS
-(define_expand "fmuls"
- [(set (reg:QI 24)
- (match_operand:QI 1 "register_operand" ""))
- (set (reg:QI 25)
- (match_operand:QI 2 "register_operand" ""))
- (parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULS))
- (clobber (reg:HI 24))])
- (set (match_operand:HI 0 "register_operand" "")
- (reg:HI 22))]
- ""
- {
- if (AVR_HAVE_MUL)
- {
- emit_insn (gen_fmuls_insn (operand0, operand1, operand2));
- DONE;
- }
- avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
- })
-
-(define_insn_and_split "fmuls_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (unspec:HI [(match_operand:QI 1 "register_operand" "a")
- (match_operand:QI 2 "register_operand" "a")]
- UNSPEC_FMULS))]
- "AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(scratch)]
- { DONE_ADD_CCC })
-
-(define_insn "*fmuls_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (unspec:HI [(match_operand:QI 1 "register_operand" "a")
- (match_operand:QI 2 "register_operand" "a")]
- UNSPEC_FMULS))
- (clobber (reg:CC REG_CC))]
- "AVR_HAVE_MUL && reload_completed"
- "fmuls %1,%2
- movw %0,r0
- clr __zero_reg__"
- [(set_attr "length" "3")])
+;; FMULSU
+(define_int_iterator FMUL [UNSPEC_FMUL UNSPEC_FMULS UNSPEC_FMULSU])
+(define_int_attr fmul [(UNSPEC_FMUL "fmul") (UNSPEC_FMULS "fmuls") (UNSPEC_FMULSU "fmulsu")])
+(define_int_attr fmul_X [(UNSPEC_FMUL "%") (UNSPEC_FMULS "%") (UNSPEC_FMULSU "")])
+(define_int_attr fmul_1 [(UNSPEC_FMUL "{r25}") (UNSPEC_FMULS "{r25}") (UNSPEC_FMULSU "{r24}")])
+(define_int_attr fmul_2 [(UNSPEC_FMUL "{r24}") (UNSPEC_FMULS "{r24}") (UNSPEC_FMULSU "{r25}")])
-(define_insn_and_split "*fmuls.call_split"
- [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULS))
- (clobber (reg:HI 24))]
- "!AVR_HAVE_MUL"
+;; "fmul" "fmuls" "fmulsu"
+(define_insn_and_split "<fmul>"
+ [(set (match_operand:HI 0 "register_operand" "={r22},{r22} ,r")
+ (unspec:HI [(match_operand:QI 1 "register_operand" "<fmul_X>{r24},<fmul_1>,a")
+ (match_operand:QI 2 "register_operand" "{r25},<fmul_2>,a")]
+ FMUL))
+ (clobber (match_scratch:HI 3 "={r24},{r24} ,X"))]
+ ""
"#"
"&& reload_completed"
[(scratch)]
- { DONE_ADD_CCC })
+ { DONE_ADD_CCC }
+ [(set_attr "isa" "no_mul,no_mul,mul")])
-(define_insn "*fmuls.call"
+;; "*fmul.call" "*fmuls.call" "*fmulsu.call"
+(define_insn "*<fmul>.call"
[(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULS))
+ (unspec:HI [(match_operand:QI 0 "register_operand" "{r24},<fmul_1>")
+ (match_operand:QI 1 "register_operand" "{r25},<fmul_2>")]
+ FMUL))
(clobber (reg:HI 24))
(clobber (reg:CC REG_CC))]
"!AVR_HAVE_MUL && reload_completed"
- "%~call __fmuls"
+ "%~call __<fmul>"
[(set_attr "type" "xcall")])
-;; FMULSU
-(define_expand "fmulsu"
- [(set (reg:QI 24)
- (match_operand:QI 1 "register_operand" ""))
- (set (reg:QI 25)
- (match_operand:QI 2 "register_operand" ""))
- (parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULSU))
- (clobber (reg:HI 24))])
- (set (match_operand:HI 0 "register_operand" "")
- (reg:HI 22))]
- ""
- {
- if (AVR_HAVE_MUL)
- {
- emit_insn (gen_fmulsu_insn (operand0, operand1, operand2));
- DONE;
- }
- avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
- })
-
-(define_insn_and_split "fmulsu_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (unspec:HI [(match_operand:QI 1 "register_operand" "a")
- (match_operand:QI 2 "register_operand" "a")]
- UNSPEC_FMULSU))]
- "AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(scratch)]
- { DONE_ADD_CCC })
-
-(define_insn "*fmulsu_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (unspec:HI [(match_operand:QI 1 "register_operand" "a")
- (match_operand:QI 2 "register_operand" "a")]
- UNSPEC_FMULSU))
+;; "*fmul_insn" "*fmuls_insn" "*fmulsu_insn"
+(define_insn "*<fmul>_insn"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (unspec:HI [(match_operand:QI 1 "register_operand" "<fmul_X>a")
+ (match_operand:QI 2 "register_operand" "a")]
+ FMUL))
+ (clobber (scratch:HI))
(clobber (reg:CC REG_CC))]
"AVR_HAVE_MUL && reload_completed"
- "fmulsu %1,%2
+ "<fmul> %1,%2
movw %0,r0
clr __zero_reg__"
[(set_attr "length" "3")])
-(define_insn_and_split "*fmulsu.call_split"
- [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULSU))
- (clobber (reg:HI 24))]
- "!AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(scratch)]
- { DONE_ADD_CCC })
-
-(define_insn "*fmulsu.call"
- [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULSU))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))]
- "!AVR_HAVE_MUL && reload_completed"
- "%~call __fmulsu"
- [(set_attr "type" "xcall")
- ])
;; Some combiner patterns dealing with bits.
#define AI inline __attribute__((always_inline))
typedef __INT8_TYPE__ int8_t;
typedef __UINT8_TYPE__ uint8_t;
typedef __INT16_TYPE__ int16_t;
typedef __UINT16_TYPE__ uint16_t;
static AI uint16_t fmul (uint8_t a, uint8_t b)
{
return __builtin_avr_fmul (a, b);
}
static AI int16_t fmuls (int8_t a, int8_t b)
{
return __builtin_avr_fmuls (a, b);
}
static AI int16_t fmulsu (int8_t a, uint8_t b)
{
return __builtin_avr_fmulsu (a, b);
}
uint16_t fun1 (char a, char b) { return fmul (a, b); }
uint16_t fun2 (char a, char b) { return fmul (b, a); }
uint16_t fun3 (char a, char b) { return fmuls (a, b); }
uint16_t fun4 (char a, char b) { return fmuls (b, a); }
uint16_t fun5 (char a, char b) { return fmulsu (a, b); }
uint16_t fun6 (char a, char b) { return fmulsu (b, a); }
uint16_t gun1 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmul (a, b);
}
uint16_t gun2 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmul (b, a);
}
uint16_t gun3 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmuls (a, b);
}
uint16_t gun4 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmuls (b, a);
}
uint16_t gun5 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmulsu (a, b);
}
uint16_t gun6 ()
{
uint8_t a, b;
__asm (";; %0 %1" : "={r24}" (a), "={r25}" (b));
return fmulsu (b, a);
}
.file "fmul.c"
__SP_H__ = 0x3e
__SP_L__ = 0x3d
__SREG__ = 0x3f
__tmp_reg__ = 0
__zero_reg__ = 1
.text
.global fun1
.type fun1, @function
fun1:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
mov r25,r22 ; 19 [c=4 l=1] movqi_insn/0
rcall __fmul ; 20 [c=8 l=1] *fmul.call/0
mov r24,r22 ; 26 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 27 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 24 [c=0 l=1] return
.size fun1, .-fun1
.global fun2
.type fun2, @function
fun2:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
mov r25,r22 ; 19 [c=4 l=1] movqi_insn/0
rcall __fmul ; 20 [c=8 l=1] *fmul.call/0
mov r24,r22 ; 26 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 27 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 24 [c=0 l=1] return
.size fun2, .-fun2
.global fun3
.type fun3, @function
fun3:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
mov r25,r22 ; 20 [c=4 l=1] movqi_insn/0
rcall __fmuls ; 21 [c=8 l=1] *fmuls.call/0
mov r24,r22 ; 27 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 28 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 25 [c=0 l=1] return
.size fun3, .-fun3
.global fun4
.type fun4, @function
fun4:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
mov r25,r22 ; 20 [c=4 l=1] movqi_insn/0
rcall __fmuls ; 21 [c=8 l=1] *fmuls.call/0
mov r24,r22 ; 27 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 28 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 25 [c=0 l=1] return
.size fun4, .-fun4
.global fun5
.type fun5, @function
fun5:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
mov r25,r22 ; 20 [c=4 l=1] movqi_insn/0
rcall __fmulsu ; 21 [c=8 l=1] *fmulsu.call/0
mov r24,r22 ; 27 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 28 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 25 [c=0 l=1] return
.size fun5, .-fun5
.global fun6
.type fun6, @function
fun6:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
mov r25,r24 ; 21 [c=4 l=1] movqi_insn/0
mov r24,r22 ; 22 [c=4 l=1] movqi_insn/0
rcall __fmulsu ; 23 [c=8 l=1] *fmulsu.call/0
mov r24,r22 ; 29 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 30 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 27 [c=0 l=1] return
.size fun6, .-fun6
.global gun1
.type gun1, @function
gun1:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
/* #APP */
; 35 "/home/gjl/fmul.c" 1
;; r24 r25
; 0 "" 2
/* #NOAPP */
rcall __fmul ; 17 [c=8 l=1] *fmul.call/0
mov r24,r22 ; 23 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 24 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 21 [c=0 l=1] return
.size gun1, .-gun1
.global gun2
.type gun2, @function
gun2:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
/* #APP */
; 42 "/home/gjl/fmul.c" 1
;; r24 r25
; 0 "" 2
/* #NOAPP */
mov r18,r25 ; 20 [c=4 l=1] movqi_insn/0
mov r25,r24 ; 21 [c=4 l=1] movqi_insn/0
mov r24,r18 ; 22 [c=4 l=1] movqi_insn/0
rcall __fmul ; 23 [c=8 l=1] *fmul.call/0
mov r24,r22 ; 29 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 30 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 27 [c=0 l=1] return
.size gun2, .-gun2
.global gun3
.type gun3, @function
gun3:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
/* #APP */
; 49 "/home/gjl/fmul.c" 1
;; r24 r25
; 0 "" 2
/* #NOAPP */
rcall __fmuls ; 18 [c=8 l=1] *fmuls.call/0
mov r24,r22 ; 24 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 25 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 22 [c=0 l=1] return
.size gun3, .-gun3
.global gun4
.type gun4, @function
gun4:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
/* #APP */
; 56 "/home/gjl/fmul.c" 1
;; r24 r25
; 0 "" 2
/* #NOAPP */
mov r18,r25 ; 21 [c=4 l=1] movqi_insn/0
mov r25,r24 ; 22 [c=4 l=1] movqi_insn/0
mov r24,r18 ; 23 [c=4 l=1] movqi_insn/0
rcall __fmuls ; 24 [c=8 l=1] *fmuls.call/0
mov r24,r22 ; 30 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 31 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 28 [c=0 l=1] return
.size gun4, .-gun4
.global gun5
.type gun5, @function
gun5:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
/* #APP */
; 63 "/home/gjl/fmul.c" 1
;; r24 r25
; 0 "" 2
/* #NOAPP */
rcall __fmulsu ; 18 [c=8 l=1] *fmulsu.call/0
mov r24,r22 ; 24 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 25 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 22 [c=0 l=1] return
.size gun5, .-gun5
.global gun6
.type gun6, @function
gun6:
/* prologue: function */
/* frame size = 0 */
/* stack size = 0 */
.L__stack_usage = 0
/* #APP */
; 70 "/home/gjl/fmul.c" 1
;; r24 r25
; 0 "" 2
/* #NOAPP */
mov r18,r25 ; 21 [c=4 l=1] movqi_insn/0
mov r25,r24 ; 22 [c=4 l=1] movqi_insn/0
mov r24,r18 ; 23 [c=4 l=1] movqi_insn/0
rcall __fmulsu ; 24 [c=8 l=1] *fmulsu.call/0
mov r24,r22 ; 30 [c=4 l=1] movqi_insn/0
mov r25,r23 ; 31 [c=4 l=1] movqi_insn/0
/* epilogue start */
ret ; 28 [c=0 l=1] return
.size gun6, .-gun6
.ident "GCC: (GNU) 17.0.0 20260528 (experimental)"
