Hi all,
This promotes Uci and Ucj from internal to public constraints. They are
already both documented publically in LLVM [1] and we've had a request
from kernel folks who would like to make use of Ucj for saving/restoring
ZA contents [2].
Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk?
Thanks,
Alex
[1] : https://llvm.org/docs/LangRef.html#supported-constraint-code-list
[2] : https://lore.kernel.org/linux-arm-kernel/ahW8Eba3SNqfVDdk@J2N7QTR9R3/
gcc/ChangeLog:
* config/aarch64/constraints.md (Uci): Drop @internal, slightly tweak
doc string.
(Ucj): Likewise.
* doc/md.texi (Machine Constraints): Document Uci and Ucj under AArch64
family.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sme/inline-asm.c: New test.
---
gcc/config/aarch64/constraints.md | 4 ++--
gcc/doc/md.texi | 8 ++++++++
.../gcc.target/aarch64/sme/inline-asm.c | 16 ++++++++++++++++
3 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/inline-asm.c
diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 829b2c949d0..847739e3270 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -22,10 +22,10 @@ (define_register_constraint "k" "STACK_REG"
"@internal The stack register.")
(define_register_constraint "Uci" "W8_W11_REGS"
- "@internal r8-r11, which can be used to index ZA.")
+ "GPRs r8-r11, can be used to index ZA.")
(define_register_constraint "Ucj" "W12_W15_REGS"
- "@internal r12-r15, which can be used to index ZA.")
+ "GPRs r12-r15, can be used to index ZA.")
(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
"@internal Registers suitable for an indirect tail call")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 94d258c3c91..f322f24ee92 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1950,6 +1950,14 @@ the meanings of that architecture's constraints.
@item k
The stack pointer register (@code{SP})
+@item Uci
+Like @code{r}, but restricted to registers 8 through 11 inclusive. Can be used
+to index ZA.
+
+@item Ucj
+Like @code{r}, but restricted to registers 12 through 15 inclusive. Can be
+used to index ZA.
+
@item w
Floating point register, Advanced SIMD vector register or SVE vector register
diff --git a/gcc/testsuite/gcc.target/aarch64/sme/inline-asm.c b/gcc/testsuite/gcc.target/aarch64/sme/inline-asm.c
new file mode 100644
index 00000000000..8b3d2f545a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme/inline-asm.c
@@ -0,0 +1,16 @@
+/* This test checks the use of the Uc[ij] constraints in inline asm. */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void ucj(unsigned v, void *p)
+{
+ asm volatile ("str za[%w0, #0], [%1]" :: "Ucj"(v), "r"(p));
+}
+
+void uci(unsigned wv)
+{
+ asm volatile ("mova { z0.d-z1.d }, za.d[%w0, #0, vgx2]" :: "Uci"(wv));
+}
+
+/* { dg-final { scan-assembler-times {str za\[w1[2-5], #0\], \[x1\]} 1 } } */
+/* { dg-final { scan-assembler-times {mova { z0\.d-z1\.d }, za\.d\[w([89]|1[01]), #0, vgx2\]} 1 } } */
