On Wed, May 27, 2026 at 4:50 PM Hongyu Wang <[email protected]> wrote:
>
> Hi,
>
> Microbenchmark performance on NovaLake/DiamondRapids shows no benefit
> from SETcc.ZU encoding on these cores. Add X86_TUNE_DISABLE_SETZUCC
> to suppress setzucc generation for DMR/NVL while keeping it enabled
> for other APX-capable targets.
>
> Bootstrapped && regtested on x86_64-pc-linux-gnu{-m32,}.
>
> Ok for trunk/backport to gcc16?
Ok.
>
> gcc/ChangeLog:
>
> * config/i386/x86-tune.def (X86_TUNE_DISABLE_SETZUCC): New.
> Enable for m_DIAMONDRAPIDS | m_NOVALAKE.
> * config/i386/i386.h (TARGET_DISABLE_SETZUCC): New define.
> * config/i386/i386.md (*setcc_<mode>_zu): Guard with
> TARGET_APX_ZU && !TARGET_DISABLE_SETZUCC.
> (*setcc_di_1, *setcc_<mode>_1_movzbl): Guard with
> (!TARGET_APX_ZU || TARGET_DISABLE_SETZUCC).
> (*setcc_qi, *setcc_qi_slp): Emit setzucc only when
> TARGET_APX_ZU && !TARGET_DISABLE_SETZUCC.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/apx-zu-4.c: New test.
> ---
> gcc/config/i386/i386.h | 3 ++-
> gcc/config/i386/i386.md | 12 +++++++-----
> gcc/config/i386/x86-tune.def | 4 ++++
> gcc/testsuite/gcc.target/i386/apx-zu-4.c | 5 +++++
> 4 files changed, 18 insertions(+), 6 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/apx-zu-4.c
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index ac3f2213e78..3b0ccc66127 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -511,7 +511,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
> ix86_tune_features[X86_TUNE_ALIGN_TIGHT_LOOPS]
> #define TARGET_SSE_REDUCTION_PREFER_PSHUF \
> ix86_tune_features[X86_TUNE_SSE_REDUCTION_PREFER_PSHUF]
> -
> +#define TARGET_DISABLE_SETZUCC \
> + ix86_tune_features[X86_TUNE_DISABLE_SETZUCC]
>
> /* Feature tests against the various architecture variations. */
> enum ix86_arch_indices {
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 063e14cb2c1..fb77b4a006c 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -19722,7 +19722,7 @@ (define_insn "*setcc_<mode>_zu"
> [(set (match_operand:SWI248 0 "register_operand" "=r")
> (match_operator:SWI248 1 "ix86_comparison_operator"
> [(reg FLAGS_REG) (const_int 0)]))]
> - "TARGET_APX_ZU"
> + "TARGET_APX_ZU && !TARGET_DISABLE_SETZUCC"
> "setzu%C1\t%b0"
> [(set_attr "type" "setcc")])
>
> @@ -19730,7 +19730,8 @@ (define_insn_and_split "*setcc_di_1"
> [(set (match_operand:DI 0 "register_operand" "=q")
> (match_operator:DI 1 "ix86_comparison_operator"
> [(reg FLAGS_REG) (const_int 0)]))]
> - "!TARGET_APX_ZU && TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
> + "(!TARGET_APX_ZU || TARGET_DISABLE_SETZUCC)
> + && TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
> "#"
> "&& reload_completed"
> [(set (match_dup 2) (match_dup 1))
> @@ -19763,7 +19764,7 @@ (define_insn_and_split "*setcc_<mode>_1_movzbl"
> [(set (match_operand:SWI24 0 "register_operand" "=q")
> (match_operator:SWI24 1 "ix86_comparison_operator"
> [(reg FLAGS_REG) (const_int 0)]))]
> - "!TARGET_APX_ZU && !TARGET_PARTIAL_REG_STALL
> + "(!TARGET_APX_ZU || TARGET_DISABLE_SETZUCC) && !TARGET_PARTIAL_REG_STALL
> && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
> "#"
> "&& reload_completed"
> @@ -19782,7 +19783,8 @@ (define_insn "*setcc_qi"
> ""
> {
> if (REG_P (operands[0])
> - && TARGET_APX_ZU)
> + && TARGET_APX_ZU
> + && !TARGET_DISABLE_SETZUCC)
> return "setzu%C1\t%0";
> else
> return "set%C1\t%0";
> @@ -19796,7 +19798,7 @@ (define_insn "*setcc_qi_slp"
> [(reg FLAGS_REG) (const_int 0)]))]
> ""
> {
> - if (TARGET_APX_ZU)
> + if (TARGET_APX_ZU && !TARGET_DISABLE_SETZUCC)
> return "setzu%C1\t%0";
> else
> return "set%C1\t%0";
> diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
> index 202b38ad50b..cfbd56f88d9 100644
> --- a/gcc/config/i386/x86-tune.def
> +++ b/gcc/config/i386/x86-tune.def
> @@ -401,6 +401,10 @@ DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
> DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs",
> m_CORE_ALL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS |
> m_ZHAOXIN)
>
> +/* X86_TUNE_DISABLE_SETZUCC: Disable SETcc with ZU suffix. */
> +DEF_TUNE (X86_TUNE_DISABLE_SETZUCC, "disable_setzucc",
> + m_DIAMONDRAPIDS | m_NOVALAKE)
> +
>
> /*****************************************************************************/
> /* 387 instruction selection tuning
> */
>
> /*****************************************************************************/
> diff --git a/gcc/testsuite/gcc.target/i386/apx-zu-4.c
> b/gcc/testsuite/gcc.target/i386/apx-zu-4.c
> new file mode 100644
> index 00000000000..0c8625792a9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/apx-zu-4.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mapxf -march=x86-64 -O2 -mtune-ctrl=disable_setzucc" } */
> +/* { dg-final { scan-assembler-not "setzu" } } */
> +
> +#include "apx-zu-3.c"
> --
> 2.31.1
>
--
BR,
Hongtao
