Add tuning definitions for the XuanTie C908 core, including a
scalar scheduler model.
The scheduler model describes the scalar integer, load/store, multiply,
divide, and floating-point pipeline resources. It is based on the
XuanTie C908 R1S0 User Manual.
This patch only models scalar scheduling. Vector scheduling is left for
future work (xt-c908v).
The scheduler model was tested on a CanMV-K230-V1.1 with CoreMark and a set
of instruction throughput tests.
The instruction throughput tests are essentially unrolled loops which
have groups of instructions (a group of adds and a group of fadd instructions
we are measuring for example) which use independent registers. For the
purpose of estimating the efficiency of scheduling such an unrolled loop,
the impact of reducing pipeline stalls on measured cycle counts is noticeable.
Each test uses aligned memory access. Before taking
measurements, the benchmark performs 20 warm-up runs. The measured test
is then executed 200 times.
On a CanMV-K230-V1.1 board, this tuning gives about a 0.8% CoreMark improvement.
The instruction throughput tests show cycle-count improvements of
about 5% to 17%.
Long-latency reservations are clamped to 7 cycles, following the existing
RISC-V scheduler modelling approach introduced by commit 8265192.
2026-06-03 Milan Tripkovic <[email protected]>
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Changed xt-c908
PIPELINE_MODEL and TUNE_INFO
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add entry
for xt-c908 design
* config/riscv/riscv.cc: New tune structure
for the xt-c908 design.
* config/riscv/riscv.md: Add xt-c908 .
Include xt-c908.md.
* config/riscv/xt-c908.md: New file.
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---
gcc/config/riscv/riscv-cores.def | 2 +-
gcc/config/riscv/riscv-opts.h | 3 +-
gcc/config/riscv/riscv.cc | 24 ++++++
gcc/config/riscv/riscv.md | 3 +-
gcc/config/riscv/xt-c908.md | 137 +++++++++++++++++++++++++++++++
5 files changed, 166 insertions(+), 3 deletions(-)
create mode 100644 gcc/config/riscv/xt-c908.md
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 416fcacdd0..4cfd924b47 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -42,7 +42,7 @@ RISCV_TUNE("sifive-p400-series", sifive_p400,
sifive_p400_tune_info)
RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
RISCV_TUNE("tt-ascalon-d8", tt_ascalon_d8, tt_ascalon_d8_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
-RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c908", xt_c908, xt_c908_tune_info)
RISCV_TUNE("xt-c908v", generic, generic_ooo_tune_info)
RISCV_TUNE("xt-c910", generic, generic_ooo_tune_info)
RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 036680117c..2a4e9260dc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -66,7 +66,8 @@ enum riscv_microarchitecture_type {
andes_45_series,
spacemit_x60,
arcv_rmx100,
- arcv_rhx100
+ arcv_rhx100,
+ xt_c908
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a2730a90ca..f0fab5033b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -836,6 +836,30 @@ static const struct riscv_tune_param andes_25_tune_info = {
true, /* prefer-agnostic. */
};
+static const struct riscv_tune_param xt_c908_tune_info= {
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_mul */
+ {COSTS_N_INSNS (7), COSTS_N_INSNS (7)}, /* fp_div */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */
+ {COSTS_N_INSNS (7), COSTS_N_INSNS (7)}, /* int_div */
+ 2, /* issue_rate */
+ 3, /* branch_cost */
+ 4, /* memory_cost */
+ 3, /* fmv_cost */
+ false, /* slow_unaligned_access */
+ false, /* vector_unaligned_access */
+ false, /* use_divmod_expansion */
+ true, /* overlap_op_by_pieces */
+ false, /* use_zero_stride_load */
+ false, /* speculative_sched_vsetvl */
+ RISCV_FUSE_NOTHING, /* fusible_ops */
+ &generic_vector_cost, /* vector cost */
+ NULL, /* function_align */
+ NULL, /* jump_align */
+ NULL, /* loop_align */
+ false, /* prefer-agnostic. */
+};
+
static const struct riscv_tune_param spacemit_x60_tune_info= {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 5f9f26ee63..46b02e6839 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -680,7 +680,7 @@
(define_attr "tune"
"generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,
tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60,
- arcv_rmx100,arcv_rhx100"
+ arcv_rmx100,arcv_rhx100,xt_c908"
(const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
;; Describe a user's asm statement.
@@ -5309,5 +5309,6 @@
(include "andes-25-series.md")
(include "andes-45-series.md")
(include "spacemit-x60.md")
+(include "xt-c908.md")
(include "arcv-rmx100.md")
(include "arcv-rhx100.md")
diff --git a/gcc/config/riscv/xt-c908.md b/gcc/config/riscv/xt-c908.md
new file mode 100644
index 0000000000..9037a362e3
--- /dev/null
+++ b/gcc/config/riscv/xt-c908.md
@@ -0,0 +1,137 @@
+;; xt_c908 DFA-based pipeline description for RISC-V targets.
+;;
+;; Approximate scalar scheduler model for XuanTie C908.
+;;
+;; This is intentionally scalar-only. Vector scheduling should be added
+;; separately for xt-c908v.
+
+(define_automaton "xt_c908")
+
+(define_cpu_unit "xt_c908_alu0,xt_c908_alu1" "xt_c908")
+(define_cpu_unit "xt_c908_lsu0,xt_c908_lsu1" "xt_c908")
+(define_cpu_unit "xt_c908_mpy" "xt_c908")
+(define_cpu_unit "xt_c908_div" "xt_c908")
+(define_cpu_unit "xt_c908_fpalu" "xt_c908")
+(define_cpu_unit "xt_c908_fdivsqrt" "xt_c908")
+
+
+(define_reservation "xt_c908_alu" "xt_c908_alu0 | xt_c908_alu1")
+(define_reservation "xt_c908_lsu" "xt_c908_lsu0 | xt_c908_lsu1")
+
+;; ----------------------------------------------------
+;; Memory (load/store)
+;; ----------------------------------------------------
+
+(define_insn_reservation "xt_c908_load" 3
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "load,fpload"))
+ "xt_c908_lsu")
+
+(define_insn_reservation "xt_c908_store" 1
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "store,fpstore"))
+ "xt_c908_lsu")
+
+;; ----------------------------------------------------
+;; Integer
+;; ----------------------------------------------------
+
+(define_insn_reservation "xt_c908_jump" 1
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "branch,jump,call,jalr,ret,trap,sfb_alu"))
+ "xt_c908_alu0")
+
+(define_insn_reservation "xt_c908_idivsi" 7
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "idiv"))
+ "xt_c908_div*7")
+
+(define_insn_reservation "xt_c908_imul" 4
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "imul"))
+ "xt_c908_mpy*2")
+
+(define_insn_reservation "xt_c908_mtc_mfc" 3
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "mtc,mfc"))
+ "xt_c908_alu")
+
+(define_insn_reservation "xt_c908_alu" 1
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
+ move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,\
+ condmove,crypto,mvpair,zicond,cpop,clmul,atomic"))
+ "xt_c908_alu")
+
+;; ----------------------------------------------------
+;; Floating point
+;; ----------------------------------------------------
+
+(define_insn_reservation "xt_c908_fcvt" 4
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "fcvt,fmove,fcvt_i2f,fcvt_f2i"))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fcmp" 4
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "fcmp"))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fadd" 3
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "fadd"))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fmulH" 3
+ (and (eq_attr "tune" "xt_c908")
+ (and (eq_attr "type" "fmul")
+ (eq_attr "mode" "HF")))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fmulSD" 4
+ (and (eq_attr "tune" "xt_c908")
+ (and (eq_attr "type" "fmul")
+ (ior (eq_attr "mode" "SF")
+ (eq_attr "mode" "DF"))))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fmaddH" 4
+ (and (eq_attr "tune" "xt_c908")
+ (and (eq_attr "type" "fmadd")
+ (eq_attr "mode" "HF")))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fmaddSD" 5
+ (and (eq_attr "tune" "xt_c908")
+ (and (eq_attr "type" "fmadd")
+ (ior (eq_attr "mode" "SF")
+ (eq_attr "mode" "DF"))))
+ "xt_c908_fpalu")
+
+(define_insn_reservation "xt_c908_fdiv" 7
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "fdiv,fsqrt"))
+ "xt_c908_fdivsqrt*7")
+
+(define_insn_reservation "xt_c908_dummy" 1
+ (and (eq_attr "tune" "xt_c908")
+ (eq_attr "type" "rdfrm,rdvl,rdvlenb,sf_vc,sf_vc_se,
+ sf_vfnrclip,sf_vqmacc,vaalu,vaesdf,vaesdm,vaesef,vaesem,
+ vaeskf1,vaeskf2,vaesz,vandn,vbrev,vbrev8,vclmul,vclmulh,
+ vclz,vcompress,vcpop,vctz,vector,vext,vfalu,vfclass,vfcmp,
+ vfcvtftoi,vfcvtitof,vfdiv,vfmerge,vfminmax,vfmov,vfmovfv,
+ vfmovvf,vfmul,vfmuladd,vfncvtbf16,vfncvtftof,vfncvtftoi,
+ vfncvtitof,vfrecp,vfredo,vfredu,vfsgnj,vfslide1down,
+ vfslide1up,vfsqrt,vfwalu,vfwcvtbf16,vfwcvtftof,
+ vfwcvtftoi,vfwcvtitof,vfwmaccbf16,vfwmul,vfwmuladd,
+ vfwredo,vfwredu,vgather,vghsh,vgmul,vialu,vicalu,vicmp,
+ vidiv,vimerge,viminmax,vimov,vimovvx,vimovxv,vimul,
+ vimuladd,vired,vislide1down,vislide1up,viwalu,viwmul,
+ viwmuladd,viwred,vlde,vldff,vldm,vldox,vldr,vlds,vldux,
+ vlsegde,vlsegdff,vlsegdox,vlsegds,vlsegdux,vmalu,vmffs,
+ vmidx,vmiota,vmov,vmpop,vmsfs,vnclip,vnshift,vrev8,vrol,
+ vror,vsalu,vsetvl,vsetvl_pre,vsha2ch,vsha2cl,vsha2ms,
+ vshift,vslidedown,vslideup,vsm3c,vsm3me,vsm4k,vsm4r,
+ vsmul,vssegte,vssegtox,vssegts,vssegtux,vsshift,vste,
+ vstm,vstox,vstr,vsts,vstux,vwsll,wrfrm,wrvxrm"))
+ "nothing")
--
2.34.1
